The PHY interface signals to the Versal adaptive SoC logic can be categorized into six groups:
- Clocking and Reset
- Command and Address
- Write Data
- Read Data
- PHY Control
- Debug
Clocking and Reset and Debug signals are described in other sections or documents. See the corresponding references. In this section, a description is given for each signal in the remaining four groups and timing diagrams show examples of the signals in use.