This section describes the Versal adaptive SoC logic interface signals and key parameters of the DDR4 PHY. The goal is to implement a “PHY Only” solution that connects your own custom Memory Controller directly to the DDR4 SDRAM generated PHY, instead of interfacing to the user interface or AXI Interface of a DDR4 SDRAM generated Memory Controller. The PHY interface takes DRAM commands, like Activate, Precharge, Refresh, etc. at its input ports and issues them directly to the DRAM bus.
The PHY does not take in “memory transactions” like the user and AXI interfaces, which translate transactions into one or more DRAM commands that meet DRAM protocol and timing requirements. The PHY interface does no DRAM protocol or timing checking. When using a PHY Only option, you are responsible for meeting all DRAM protocol requirements and timing specifications of all DRAM components in the system.
The PHY runs at the system clock frequency, or 1/4 of the DRAM clock frequency. The PHY therefore accepts four DRAM commands per system clock and issues them serially on consecutive DRAM clock cycles on the DRAM bus. In other words, the PHY interface has four command slots: slots 0, 1, 2, and 3, which it accepts each system clock. The command in slot position 0 is issued on the DRAM bus first, and the command in slot 3 is issued last. The PHY does have limitations as to which slots can accept read and write CAS commands. For more information, see the CAS Command Timing Limitations section. Except for CAS commands, each slot can accept arbitrary DRAM commands.
The PHY Versal adaptive SoC logic interface
has an input port for each pin on a DDR4
bus. Each PHY command/address input port has a width that is eight times wider than its
corresponding DRAM bus pin. For example, a DDR4 bus has one act_n pin, and
the PHY has an 8-bit mc_ACT_n input port. Each pair of
bits in the mc_ACT_n port corresponds to a "command
slot." The two LSBs are slot0 and the two MSBs are slot3. The PHY address input port for
a DDR4 design with 18 address pins is 144
bits wide, with each byte corresponding to the four command slots for one DDR4 address pin. There are two bits for each
command slot in each input port of the PHY.
This is due to the underlying design of the PHY and its support for double data rate data buses. But as the DRAM command/address bus is single data rate, you must always drive the two bits that correspond to a command slot to the same value. See the following interface tables for additional descriptions and examples in the timing diagrams that show how bytes and bits correspond to DRAM pins and command slots.
The PHY interface has read and write data ports with eight bits for each DRAM DQ pin. Each port bit represents one data bit on the DDR DRAM bus for a BL8 burst. Therefore one BL8 data burst for the entire DQ bus is transferred across the PHY interface on each system clock. The PHY only supports BL8 data transfers. The data format is the same as the user interface data format. For more information, see the PHY section.
The PHY interface also has several control signals that you must drive and/or respond to when a read or write CAS command is issued. The control signals are used by the PHY to manage the transfer of read and write data between the PHY interface and the DRAM bus. See the following signal tables and timing diagrams.
Your custom Memory Controller must wait until the PHY output
calDone is asserted before sending any DRAM commands to the PHY.
The PHY initializes and trains the DRAM before asserting calDone. For
more information on the PHY internal structures and training algorithms, see the PHY
section. After calDone is asserted, the PHY is ready to accept any DRAM
commands.
The only required DRAM or PHY commands are related to VT tracking and DRAM refresh/ZQ. These requirements are detailed in VT Tracking and Refresh and ZQ sections.