All PHY parameters are configured by the DDR4 SDRAM software. The table describes the PHY parameters. These parameter values must not be modified in the DDR4 SDRAM generated designs. The parameters are set during core generation. The core must be regenerated to change any parameter settings.
| Parameter Name | Default Value | Allowable Values | Description |
|---|---|---|---|
| ADDR_WIDTH | 18 | 18.. 17 | Number of DRAM Address pins |
| BANK_WIDTH | 2 | 2 | Number of DRAM Bank Address pins |
| BANK_GROUP_WIDTH | 2 | 2.. 1 | Number of DRAM Bank Group pins |
| CK_WIDTH | 1 | 2.. 1 | Number of DRAM Clock pins |
| CKE_WIDTH | 1 | 2.. 1 | Number of DRAM CKE pins |
| CS_WIDTH | 1 | 2.. 1 | Number of DRAM CS pins |
| ODT_WIDTH | 1 | 4.. 1 | Number of DRAM ODT pins |
| DRAM_TYPE | “DDR4” | “DDR4” | DRAM Technology |
| DQ_WIDTH | 16 | Minimum = 8 Must be multiple of 8 |
Number of DRAM DQ pins in the channel |
| DQS_WIDTH | 2 | Minimum = 1 x8 DRAM - 1 per DQ byte x4 DRAM - 1 per DQ nibble |
Number of DRAM DQS pins in the channel |
| DM_WIDTH | 2 | Minimum = 0 x8 DRAM - 1 per DQ byte x4 DRAM - 0 |
Number of DRAM DM pins in the channel |
| DATA_BUF_ADDR_WIDTH | 5 | 5 | Number of data buffer address bits stored for a read or write transaction |
| ODTWR | 0x8421 | 0xFFFF .. 0x0000 | Reserved for future use |
| ODTWRDEL | 8 | Set to CWL | Reserved for future use |
| ODTWRDUR | 6 | 7.. 6 | Reserved for future use |
| ODTRD | 0x0000 | 0xFFFF.. 0x0000 | Reserved for future use |
| ODTRDDEL | 11 | Set to CL | Reserved for future use |
| ODTRDDUR | 6 | 7.. 6 | Reserved for future use |
|
ODTWR0DEL ODTWR0DUR ODTRD0DEL ODTRD0DUR ODTNOP |
N/A | N/A | Reserved for future use |
| MR0 | 0x630 | Legal SDRAM configuration | DRAM MR0 setting |
| MR1 | 0x101 | Legal SDRAM configuration | DRAM MR1 setting |
| MR2 | 0x10 | Legal SDRAM configuration | DRAM MR2 setting |
| MR3 | 0x0 | Legal SDRAM configuration | DRAM MR3 setting |
| MR4 | 0x0 | Legal SDRAM configuration | DRAM MR4 setting. DDR4 only. |
| MR5 | 0x400 | Legal SDRAM configuration | DRAM MR5 setting. DDR4 only. |
| MR6 | 0x800 | Legal SDRAM configuration | DRAM MR6 setting. DDR4 only. |
| SLOT0_CONFIG | 0x1 | 0x1 0x3 0x5 0xF |
For more information, see the SLOT0_CONFIG section. |
| SLOT1_CONFIG | 0x0 | 0x0 0x2 0xC 0xA |
For more information, see the SLOT0_CONFIG section. |
| SLOT0_FUNC_CS | 0x1 | 0x1 0x3 0x5 0xF |
Memory bus CS_n pins used to send all DRAM commands including MRS to
memory. Each bit of the parameter represents 1-bit of the CS_n bus, for
example, the LSB indicates CS_n[0], and the MSB indicates CS_n[3]. For
DIMMs this parameter specifies the CS_n pins connected to DIMM slot
0. Note: slot 0 used here should not be confused with the
"command slot0" term used in the description of the PHY
command/address interface.
|
| SLOT1_FUNC_CS | 0x0 | 0x0 0x2 0xC 0xA |
See the SLOT0_FUNC_CS description. The only difference is that SLOT1_FUNC_CS specifies CS_n pins connected to DIMM slot 1. |
| REG_CTRL | OFF | ON OFF |
Enable RDIMM RCD initialization and calibration |
| CA_MIRROR | OFF |
ON OFF |
Enable Address mirroring. This parameter is set to ON for the DIMMs that support address mirroring. |
| DDR4_REG_RC03 | 0x30 | Legal RDIMM RCD configuration | RDIMM RCD control word 03 |
| DDR4_REG_RC04 | 0x40 | Legal RDIMM RCD configuration | RDIMM RCD control word 04 |
| DDR4_REG_RC05 | 0x50 | Legal RDIMM RCD configuration | RDIMM RCD control word 05 |
| tCK | 938 | Minimum 833 | DRAM clock period in ps |
| tXPR | 72 | Minimum 1. DRAM tXPR specification in system clocks |
See JEDEC DDR SDRAM specification. |
| tMOD | 6 | Minimum 1. DRAM tMOD specification in system clocks |
See JEDEC DDR SDRAM specification. |
| tMRD | 2 | Minimum 1. DRAM tMRD specification in system clocks |
See JEDEC DDR SDRAM specification. |
| tZQINIT | 256 | Minimum 1. DRAM tZQINIT specification in system clocks |
See JEDEC DDR SDRAM specification. |
| TCQ | 100 | 100 | Flop clock to Q in ps. For simulation purposes only. |
| EARLY_WR_DATA | “OFF” | OFF | Reserved for future use |
| EXTRA_CMD_DELAY | 0 | 2.. 0 | Added command latency in system clocks. Added command latency is required for some configurations. See details in CL/CWL section. |
| ECC | “OFF” | OFF | Enables early wrDataEn timing for DDR4 SDRAM generated controllers when set to ON. PHY only designs must set this to OFF. |
| DM_DBI | “DM_NODBI” | “NONE” “DM_NODBI” “DM_DBIRD” “NODM_DBIWR” “NODM_DBIRD” “NODM_DBIWRRD” “NODM_NODBI” |
DDR4 DM/DBI configuration. For details, see the DM_DBI PHY Parameters section. |
| USE_CS_PORT | 1 | 0 = no CS_n pins 1 = CS_n pins used |
Controls whether or not CS_n pins are connect to DRAM. If there are no CS_n pins the PHY initialization and training logic issues NOPs between DRAM commands. If there are no CS_n pins, The DRAM chip select pin (CS#) must be tied Low externally at the DRAM. |
| DRAM_WIDTH | 8 | 16, 8, 4 | DRAM component DQ width |
| RANKS | 1 | 4, 2, 1 | Number of ranks in the memory subsystem |
| nCK_PER_CLK | 4 | 4 | Number of DRAM clocks per system clock |
| C_FAMILY | “kintexu” | "kintexu" "virtexu" |
Device information used by MicroBlaze controller in the PHY. |
| BYTES | 4 | Minimum 3 | Number of XPHY "bytes" used for data, command, and address |
| DBYTES | 2 | Minimum 1 | Number of bytes in the DRAM DQ bus |
| IOBTYPE | {39'b001_001_001_001_001_101_101_001_001_001_001_001_001, 39'b001_001_001_001_001_001_001_001_001_001_001_001_001, 39'b000_011_011_011_011_111_111_011_011_011_011_001_011, 39'b001_011_011_011_011_111_111_011_011_011_011_001_011} |
3'b000 = Unused pin 3'b 001 = Single-ended output 3'b 010 = Single-ended input 3'b011 = Single-ended I/O 3'b100 = Unused pin 3'b 101 = Differential Output 3'b 110 = Differential Input 3'b 111 = Differential INOUT |
IOB setting |
| PLL_WIDTH | 1 | DDR4 SDRAM generated values | Number of PLLs |
| CLKOUTPHY_MODE | "VCO_2X" | VCO_2X | Determines the clock output frequency based on the VCO frequency for the BITSLICE_CONTROL block |
| PLLCLK_SRC | 0 | 0 = pll_clk0 1 = pll_clk1 |
XPHY PLL clock source |
| DIV_MODE | 0 | 0 = DIV4 1 = DIV2 |
XPHY controller mode setting |
| DATA_WIDTH | 8 | 8 | XPHY parallel input data width |
| CTRL_CLK | 0x3 | 0 = Internal, local div_clk used 1 = External RIU clock used |
Internal or external XPHY clock for the RIU |
| INIT | {(15 × BYTES){1'b1}} | 1'b0 1'b1 |
3-state bitslice OSERDES initial value |
| RX_DATA_TYPE | {15'b000000_00_00000_00, 15'b000000_00_00000_00, 15'b011110_10_11110_01, 15'b011110_10_11110_01} |
2'b00 = None 2'b01 = DATA(DQ_EN) 2'b10 = CLOCK(DQS_EN) 2'b11 = DATA_AND_CLOCK |
XPHY bitslice setting |
| TX_OUTPUT_PHASE_90 | {13'b1111111111111, 13'b1111111111111, 13'b0000011000010, 13'b1000011000010} |
1'b0 = No offset 1'b1 = 90° offset applied |
XPHY setting to apply 90° offset on a given bitslice |
| RXTX_BITSLICE_EN | {13'b1111101111111, 13'b1111111111111, 13'b0111101111111, 13'b1111101111111} |
1'b0 = No bitslice 1'b1 = Bitslice enabled |
XPHY setting to enable a bitslice |
| NATIVE_ODLAY_BYPASS | {(13 × BYTES){1'b0}} | 1'b0 = FALSE 1'b1 = TRUE (Bypass) |
Bypass the ODELAY on output bitslices |
| EN_OTHER_PCLK | {BYTES{2'b01}} | 1'b 0 = FALSE (not used) 1'b 1 = TRUE (used) |
XPHY setting to route capture clock from other bitslice |
| EN_OTHER_NCLK | {BYTES{2'b01}} | 1'b 0 = FALSE (not used) 1'b 1 = TRUE (used) |
XPHY setting to route capture clock from other bitslice |
| RX_CLK_PHASE_P | {{(BYTES - DBYTES){2'b00}}, {DBYTES{2'b11}}} | 2'b00 for Address/Control, 2'b11 for Data |
XPHY setting to shift the read clock DQS_P by 90° relative to the DQ |
| RX_CLK_PHASE_N | {{(BYTES - DBYTES){2'b00}}, {DBYTES{2'b11}}} | 2'b00 for Address/Control, 2'b11 for Data |
XPHY setting to shift the read clock DQS_N by 90° relative to the DQ |
| TX_GATING | {{(BYTES - DBYTES){2'b00}}, {DBYTES{2'b11}}} | 2'b00 for Address/Control, 2'b11 for Data |
Write DQS gate setting for the XPHY |
| RX_GATING | {{(BYTES - DBYTES){2'b00}}, {DBYTES{2'b11}}} |
2'b00 for Address/Control, 2'b11 for Data |
Read DQS gate setting for the XPHY |
| EN_DYN_ODLY_MODE | {{(BYTES - DBYTES){2'b00}}, {DBYTES{2'b11}}} | 2'b00 for Address/Control, 2'b11 for Data |
Dynamic loading of the ODELAY by XPHY |
| BANK_TYPE | "HP_IO" | "HP_IO" "HR_IO" |
Indicates whether selected bank is HP or HR |
| SELF_CALIBRATE | {(2 × BYTES){1'b0}} | {(2 × BYTES){1'b0}} for simulation, {(2 × BYTES){1'b1}} for hardware |
BISC self calibration |
| BYPASS_CAL | "FALSE" | "TRUE" for simulation, "FALSE" for hardware | Flag to turn calibration ON/OFF |
| CAL_WRLVL | "FULL" | "FULL" | Flag for calibration, write-leveling setting |
| CAL_DQS_GATE | "FULL" | "FULL" | Flag for calibration, DQS gate setting |
| CAL_RDLVL | "FULL" | "FULL" | Flag for calibration, read training setting |
| CAL_WR_DQS_DQ | "FULL" | "FULL" | Flag for calibration, write DQS-to-DQ setting |
| CAL_COMPLEX | "FULL" | "SKIP", "FULL" | Flag for calibration, complex pattern setting |
| CAL_RD_VREF | "SKIP" | "SKIP", "FULL" | Flag for calibration, read V REF setting |
| CAL_WR_VREF | "SKIP" | "SKIP", "FULL" | Flag for calibration, write V REF setting |
| CAL_JITTER | "FULL" | "FULL", "NONE" | Reserved for verification. Speed up calibration simulation. Must be set to "FULL" for all hardware test cases. |
| t200us | 53305 decimal | 0x3FFFF.. 1 | Wait period after BISC complete to DRAM reset_n deassertion in system clocks |
| t500us | 133263 decimal | 0x3FFFF.. 1 | Wait period after DRAM reset_n deassertion to CKE assertion in system clocks |