Periodic Reads - 1.0 English

Versal Adaptive SoC Soft DDR4 SDRAM Memory Controller LogiCORE IP Product Guide (PG353)

Document ID
PG353
Release Date
2023-10-18
Version
1.0 English

The Versal adaptive SoC DDR PHY requires at least one DRAM RD or RDA command to be issued every 1 µs. This requirement is described in the User Interface section. If this requirement is not met by the transaction pattern at the UI, the controller detects the lack of reads and injects a read transaction into Group FSM0. This injected read is issued to the DRAM following the normal mechanisms of the controller issuing transactions. The key difference is that no read data is returned to the UI. This is wasted DRAM bandwidth.

User interface patterns with long strings of write transactions are affected the most by the PHY periodic read requirement. Consider a pattern with a 50/50 read/write transaction ratio, but organized such that the pattern alternates between 2 µs bursts of 100% page hit reads and 2 µs bursts of 100% page hit writes. There is at least one injected read in the 2 µs write burst, resulting in a loss of efficiency due to the read command and the turnaround time to switch the DRAM and DDR bus from writes to reads back to writes. This 2 µs alternating burst pattern is slightly more efficient than alternating between reads and writes every 1 µs. A 1 µs or shorter alternating pattern would eliminate the need for the controller to inject reads, but there would still be more read-write turnarounds.

Bus turnarounds are expensive in terms of efficiency and should be avoided if possible. Long bursts of page hit writes, > 2 µs in duration, are still the most efficient way to write to the DRAM, but the impact of one write-read-write turnaround each 1 µs must be taken into account when calculating the maximum write efficiency.