Pin and Bank Rules - 1.0 English

Versal Adaptive SoC Soft DDR4 SDRAM Memory Controller LogiCORE IP Product Guide (PG353)
Document ID
PG353
Release Date
2023-10-18
Version
1.0 English
The rules are for single and multi-rank memory interfaces.
Important: The Versal adaptive SoC soft memory IP can only use XPIO pins that are fully fabric accessible. Refer to the package file to determine XPIO pins that are fully fabric accessible. The XPIO pins/Banks in a Versal device that are not fabric accessible are called shadow pins/Banks.
  • Address/control means cs_n, ras_n (a16), cas_n (a15), we_n (a14), ba, bg, ck, cke, a, odt, act_n, parity, and alert_n (valid for RDIMMs and LRDIMMs only). Multi-rank systems have one cs_n, cke, odt, and one ck pair per rank.
  • Each Bank has nine nibbles numbered 0 to 8. Two consecutive nibbles in a bank are paired to form a nibble pair. For example, 0-1, 2-3, 4-5, and 6-7 are the four nibble pairs in a bank.
  • Pins in a nibble are numbered 0 to 5. For example in the package pin name IO_L0N_XCC_N0P1_M0P1_700, N0P1 indicates pin 1 of nibble 0 in bank 700.
  • An interface can span a maximum of three contiguous banks.
  • Maximum component limit for a component interface is nine. This restriction is not applicable for DIMMs.
  • Skipping banks is not allowed. However, skipping nibbles is allowed.
  • Maximum data width supported is 72.
    • Supported data widths for (x4): 8, 16, 24, and 32 with maximum of eight components.
    • Supported data widths for (x8): 8, 16, 24, 32, 40, 48, 56, 64, and 72 with maximum of nine components.
    • Supported data widths for (x16): 8, 16, 24, 32, 40, 48, 56, 64, and 72 with maximum of five components.
Note: There are two XPLLs per bank and the controller uses one XPLL in every bank that is being used by the interface.
  1. dqs, dq, and dm/dbi location.
    1. DQS_t/c must be located on the dedicated DQS pair in a nibble with DQS_t on pin-0 and DQS_c on pin-1.
    2. DQ pins must be placed only on 2, 3, 4, and 5 pins.
    3. DQ’s associated with a DQS must be placed within the same nibble pair.
    4. DM/DBI associated with a DQS must be placed only on the available pin-0 of a nibble pair. When DM/DBI is not used, pin-0 cannot be used for any other memory interface pin except RESET_n and ALERT_n.
    5. x8 components and DIMMs:
      • All DQ pins and DM pin associated with a DQS must be placed within a nibble pair (0-1, 2-3, 4-5, or 6-7).
      • Swap of any byte with any other byte is allowed.
    6. x4 components and DIMMs:
      • All DQs associated with a DQS must be placed within a nibble.
    7. All nibbles except nibble 8 in a bank can be used for Data group pins.

      Consider x16 part with data width of 32 and all data bytes are allocated in a single bank. In such cases, DQS needs to be mapped as given in the DQS Mapping for x16 Component table.

      In the DQS Mapping for x16 Component table, the Bank-Byte and Selected Memory Data Bytes indicate byte allocation in the I/O pin planner. The following example is given for one of the generated configuration in the I/O pin planner. Based on pin allocation, DQ byte allocation might vary.

      DQS Allocated (in IP on the Versal adaptive SoC) indicates DQS that is allocated on the Versal adaptive SoC end. Memory device mapping indicates how DQS needs to be mapped on the memory end.

      Table 1. DQS Mapping for x16 Component
      Bank-Byte Selected Memory Data Bytes DQS Allocated (in IP on Versal Adaptive SoC) Memory Device Mapping
      BankX_BYTE3 DQ[0-7] DQS0 Memory Device 0 – LDQS
      BankX_BYTE2 DQ[8-15] DQS1 Memory Device 0 – UDQS
      BankX_BYTE1 DQ[16-23] DQS2 Memory Device 1 – LDQS
      BankX_BYTE0 DQ[24-31] DQS3 Memory Device 1 – UDQS
  2. Nibble pairs can be configured as either data or address/control. No data signals (DQS, DQ, DM/DBI) can be in a nibble pair that is configured for address/control. Only pin-1 (in x8 components/DIMMs) can be used for the address/control in data nibbles.
  3. Address/control signals can be placed on any of the pins in a nibble and all nibbles in a bank can be used for Address/Control. All pins of Address/control group must be contained within the same bank.
  4. A CK pair must be placed on a PN pin pair within the Address/Control bank. For multi-rank devices, all CK pairs can be placed within a single nibble or spread across multiple nibbles. Here is the list of allowed nibble pins for CK.
    • DDR4 component, UDIMM, SODIMM: CK_t/_c on pin pairs 0/1, 2/3 or 4/5.
    • DDR4 RDIMM/LRDIMM: CK_t/_c on pin pairs 2/3 or 4/5 (not on 0/1).
  5. The IO_VP pin is an additional bank pin that is used as a reference to calibrate internal on-die termination (DCI). This pin must be externally connected to a 240Ω resistor on the PCB and pulled up to the bank VCCO voltage. DCI is required for this interface. All rules for the DCI in the Versal Adaptive SoC SelectIO Resources Architecture Manual (AM010) must be followed.
    Recommended: AMD strongly recommends that the DCIUpdateMode option is kept with the default value of ASREQUIRED so that the DCI circuitry is allowed to operate normally.
  6. RESET_n and ALERT_n must be placed in XP banks and must be placed on same side of banks where interface is placed, Lets say, all memory interface pins are placed on bottom side banks of device, then RESET_n and ALERT_n must be placed on bottom side of device and must not be placed on top banks of device.
  7. Banks can be shared between two controllers.
    1. Each nibble is dedicated to a specific controller (except for RESET_n). A nibble cannot be shared across two controllers
    2. No nibble interleaving is allowed. For example, with controllers A and B, “AABB” is allowed but not “ABAB”.
  8. All I/O banks used by the memory interface must be on a single side of the device, either top or bottom.
  9. Input clock for the XPLL in the memory interface must come from a GCIO pair.
    • Three bank memory interface: Input clock for XPLL must come from any GCIO pair within the three I/O banks.
    • Two bank memory interface: Input clock for XPLL must come from any GCIO pair within the two I/O banks or adjacent I/O banks.
    • One bank memory interface: Input clock for XPLL must come from any GCIO pair within its own I/O bank or adjacent I/O banks.
    Information on the clock input specifications can be found in the AC and DC Switching Characteristics data sheets (LVDS input requirements and XPLL requirements should be considered). For more information, see the Clocking section.
  10. The par input for command and address parity and the TEN input for Connectivity Test Mode are not supported by this interface. Consult the memory vendor for information on the proper connection for these pins when not used. For more information on parity errors, see the Address Parity section.
  11. For all other DRAM/DIMM pins that are not mentioned in this section, for example, SAx, SCL, SDA, contact the memory vendor for proper connectivity.
Important: Component interfaces should be created with the same component for all components in the interface. x16 components have a different number of bank groups than the x8 components. For example, a 72-bit wide component interface should be created by using nine x8 components or five x16 components where half of one component is not used. Four x16 components and one x8 component is not permissible.
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