Port Descriptions - 1.0 English

There are three port categories at the top-level of the memory interface core called the “user design.”

• The first category is the memory interface signals that directly interfaces with the SDRAM. These are defined by the JEDEC specification.
• The second category is the application interface signals. These are described in the Protocol Description section.
• The third category includes other signals necessary for proper operation of the core. These include the clocks, reset, and status signals from the core. The clocking and reset signals are described in their respective sections.

  The active-High init_calib_complete signal indicates that the initialization and calibration are complete and that the interface is now ready to accept commands for the interface.

For a PHY layer only solution, the top-level application interface signals are replaced with the PHY interface. These signals are described in the PHY Only Interface section.

The signals that interface directly with the SDRAM and the clocking and reset signals are the same as for the Memory Controller solution.