- Maximizes the DQ eye by removing skew and OCV effects using per bit read DQ deskew.
- Sweeps DQS across all DQ bits and finds the center of the data eye using both easy (Multi-Purpose register data pattern) and complex data patterns. Centering of the data eye is completed for both the DQS and DQS#.
- Post calibration, continuously maintains the relative delay of DQS versus DQ
across the VT range.
During the per bit deskew step, the toggling
01010101MPR pattern is continuously read back. Parallel increments of PQTR and NQTR are performed until the true and complement of the internal read clock registers valid data on every bit in its nibble. This is followed by parallel increments of IDELAY taps for each DQ bit until invalid data is registered for each bit. At the end of this step, the DQ bits are internally deskewed to the left edge of the incoming DQS.During the DQS centering step, the toggling
01010101MPR pattern is continuously read back. Parallel increments of PQTR and NQTR are performed until the true and complement of the internal read clock registers invalid to valid data on any bit in its nibble. This transition is recorded as the left edge of the valid window. Parallel increments of PQTR and NQTR continue until the true and complement of the internal read clock registers valid to invalid data on any bit in its nibble. This value is recorded as the right edge of the valid window. The center value is computed and loaded sequentially to all nibble PQTRs and NQTRs.After completion of read DQS centering, a sanity check is performed to ensure the DQS is indeed in the valid data window.
Read Leveling is performed over multiple stages to maximize the data eye and center the
internal read sampling clock in the read DQ window for robust sampling. To perform this,
Read Leveling performs the following sequential steps: