Read Leveling Calibration Overview - 1.0 English

Versal Adaptive SoC Soft DDR4 SDRAM Memory Controller LogiCORE IP Product Guide (PG353)

Document ID
PG353
Release Date
2023-10-18
Version
1.0 English

After the gate has been trained and Write Leveling has completed, the next step is to ensure reliable capture of the read data with the DQS. This stage of Read Leveling is divided into two phases, Per-Bit DQ Deskew and Read DQS Centering. Read Leveling uses the DDR4 Multi Purpose Register (MPR). The MPR contains a pattern that can be used to train the read DQS and DQ for read capture.

To perform per-bit deskew, a repeating pattern available through DDR4 MPR is read back to back. When per-bit deskew is complete, the same simple repeating pattern available through DDR4 MPR is used to center the DQS in the DQ read eye.

The DQS strobe passes through gate logic before the start of DQ data sampling. The gate logic drives PDQS and NDQS out of the input DQS strobe on per-nibble basis (four DQ bits per PDQS/NDQS). The XPHY provides separate delay elements PQTR/NQTR (2 to 3 ps per tap, 512 total) for the PDQS /NDQS to clock the rising and falling edge DQ data (PDQS for rising edge, NDQS for falling edge). This allows the algorithm to center the rising and falling edge DQS strobe independently to ensure more margin when dealing with DCD. The data captured in the PDQS clock domain is transferred to the NDQS clock domain before being sent to the read FIFO and to the general interconnect clock domain.

Due to this transfer of clock domains, the PDQS and NDQS clocks must be roughly 180° out of phase. This relationship between the PDQS/NDQS clock paths is set up as part of the BISC start-up routine, and thus calibration needs to maintain this relationship as part of the training (BRAM_BISC_ALIGN_PQTR, BRAM_BISC_ALIGN_NQTR, BRAM_BISC_PQTR, BRAM_BISC_NQTR).