The following table shows the revision history for this document.
| Section | Revision Summary |
|---|---|
| 10/18/2023 Version 1.0 | |
| Features | Added densities for LRDIMMs, RDIMMs, SODIMMs, and UDIMMs. |
| No Buffer System Clock Option | Added section. |
| Pin and Bank Rules | Updated #9 description. |
| Test Bench | Added chapter. |
| 11/03/2021 Version 1.0 | |
| Overall PHY Architecture | Updated 0x3E description. |
| Customizing and Generating the Core | Added note. |
| DDR4 Advanced Options Tab | Updated figure. |
| Traffic Generator | Added section. |
| Debug Signals | Debug ILA core update. |
| General Checks | Updated table descriptions. |
| Calibration Stages | Updated figure and subsections. |
| Debug Signals | Debug ILA core update. |
| DDR4 cal_r*_status Decoding | Updated Bits[7:4] |
| XSDB Memory IP GUI | Updated figures. |
| Understanding Calibration Status | Added 0x4-0x9 to CAL_POINTER. |
| Debug | Updated figure in all Debug sections. |
| Hardware Measurements | Updated General Checks description. |
| Expected Results | Removed error description. |
| XSDB Registers of Interest during Read DQS Centering Calibration | Updated figure. |
| Hardware Measurements | Removed continuous loop description. |
| Hardware Measurements | Removed continuous loop description. |
| Debugging Read DQS to DQ/DBI Centering Complex Failures | Added section. |
| Debugging Write DQS to DQ/DBI Centering Complex Failures | Added section. |
| Analyzing Read and Write Margin | Updated figures. |
| 09/24/2021 Version 1.0 | |
| General updates | Editorial updates only. No technical content updates. |
| 12/04/2020 Version 1.0 | |
| Initial release. | N/A |