Setting Additive Latency for PHY_ONLY Designs - 1.0 English

Versal Adaptive SoC Soft DDR4 SDRAM Memory Controller LogiCORE IP Product Guide (PG353)
Document ID
PG353
Release Date
2023-10-18
Version
1.0 English

For DDR4, the default value of Additive Latency is set to 0. This can be changed through the Tcl command using the user parameter AL_SEL for any PHY_ONLY (Physical Layer Only and Physical Layer Ping Pong designs). The table shows the AL_SEL user parameter information.

Table 1. Additive Latency User Parameter
User Parameter Value Format Default Value Possible Values

(Non-3DS Memories)

 Possible Values

(3DS Memories)
AL_SEL String 0 0 – Additive Latency = 0

CL-1 – Additive Latency = CL - 1

CL-2 – Additive Latency = CL - 2

 0 – Additive Latency = 0

CL-2 – Additive Latency = CL - 2

CL-3 – Additive Latency = CL - 3

Follow these steps to change the Additive Latency value.

  1. Generate DDR4 PHY_ONLY IP.
  2. In the Generate Output Products option, do not select Generate instead select Skip.
  3. Set the Additive Latency value by running the following command on the Tcl console:
    set_property -dict [list config.AL_SEL <value_to_be_set>] [get_ips <ip_name>]

    For example:

    set_property -dict [list config.AL_SEL CL-1] [get_ips ddr4_0]
  4. Generate output files by selecting Generate Output Products after right-clicking IP.

The generated output files have the Burst Type value set as per the selected value.