Setting Timing Options - 1.0 English

Versal Adaptive SoC Soft DDR4 SDRAM Memory Controller LogiCORE IP Product Guide (PG353)

Document ID
PG353
Release Date
2023-10-18
Version
1.0 English

The DDR4 interface is on the edge of meeting timing for certain configurations. Due to controller complexity, designs are failing in timing with levels of logic from eight to 11 in controller modules (u_ddr_mc instance). To meet timing for such cases, Tcl command options are supported. These Tcl commands are supported for Controller/PHY mode of the Controller and Physical Layer. Based on the Tcl command set in the console, a few RTL parameters are going to change which are listed in the following table. These parameters are valid for all DDR4 designs.

Table 1. Parameter Values Based on Tcl Command Option
Parameters Default Better timing, +4tCK Latency

(TIMING_OP1 Tcl Option)

Best timing, +4 to +8tCK Latency Depending on Transaction Pattern

(TIMING_OP2 Tcl Option)

CAS_FIFO_BYPASS ON ON OFF
PER_RD_PERF 1’b1 1’b1 1’b0
TXN_FIFO_BYPASS ON OFF OFF
TXN_FIFO_PIPE OFF ON ON

The table shows the default values for the four parameters. These parameters can be changed through the Tcl command using user parameter TIMING_OP1 or TIMING_OP2 for Controller/PHY mode of the Controller and Physical Layer. These Tcl options are not valid for any PHY_ONLY (Physical Layer Only and Physical Layer Ping Pong) designs.