The example design provides a synthesizable test bench to generate a fixed simple data
pattern. DDR4 SDRAM generates the Simple Traffic Generator (STG) module
as example_tb for native interface and example_tb_phy for
PHY only interface. The STG native interface generates 100 writes and 100 reads. The STG PHY
only interface generates 10 writes and 10 reads.
The example design can be simulated using one of the methods in the following sections.
Recommended: If a custom wrapper is used to simulate the example design, the
following parameter should be used in the custom wrapper:
parameter SIMULATION =
"TRUE"
The parameter SIMULATION is used to disable the calibration during simulation.