Stable 0 Confirmation Before Third Edge of DQS - 1.0 English

Versal Adaptive SoC Soft DDR4 SDRAM Memory Controller LogiCORE IP Product Guide (PG353)

Document ID
PG353
Release Date
2023-10-18
Version
1.0 English

Both the DQS strobe and the sampling clock can have jitter in relation to one another. For example, when they are lined up each sample can have a different result compared to the previous sample. Therefore, the fine search must begin in an area where all samples return a 0 so it is relatively stable, as shown below.

Figure 1. DQS Gate Fine Adjustment, Sample a 0

Confirmation of stable 0 before the third edge of DQS is required before starting the search of noise window of third edge of DQS. Confirmation of the stable 0 tells that fine tap increment will start from left most edge of the noise.

For confirming the stable 0 few fine taps are incremented and if it still sees stable 0 for all the fine taps then it means it is in the stable 0 region before the noise of 0 to 1 transaction. If it does not find the stable 0 this way then one coarse tap is decremented for that byte, and stable 0 is confirmed again. If it does not find stable 0 even after decrementing coarse tap, it indicates error.