| Status Registers | I/O | Width | Description |
|---|---|---|---|
| vio_tg_status_state | O | 4 | Traffic Generator state machine state |
| vio_tg_status_err_bit_valid | O | 1 | Intermediate error detected. Used as trigger to detect read error. |
| vio_tg_status_err_bit | O | APP_DATA_WIDTH | Intermediate error bit mismatch. Bitwise mismatch pattern. |
| vio_tg_status_err_addr | O | APP_DATA_WIDTH | Intermediate error address. Address location of failed read. |
| vio_tg_status_exp_bit_valid | O | 1 | Expected read data valid |
| vio_tg_status_exp_bit | O | APP_DATA_WIDTH | Expected read data |
| vio_tg_status_read_bit_valid | O | 1 | Memory read data valid |
| vio_tg_status_read_bit | O | APP_DATA_WIDTH | Memory read data |
| vio_tg_status_first_err_bit_valid | O | 1 | If vio_tg_err_chk_en is set to
1, first_err_bit_valid is set to 1 when first mismatch error is
encountered. This register is not overwritten until vio_tg_err_clear, vio_tg_err_continue, vio_tg_restart is triggered. |
| vio_tg_status_first_err_bit | O | APP_DATA_WIDTH | If vio_tg_status_first_err_bit_valid is set to 1, error mismatch bit pattern is stored in this register. |
| vio_tg_status_first_err_addr | O | APP_DATA_WIDTH | If vio_tg_status_first_err_bit_valid is set to 1, error address is stored in this register. |
| vio_tg_status_first_exp_bit_valid | O | 1 | If vio_tg_err_chk_en is set to 1, this represents expected read data valid when first mismatch error is encountered. |
| vio_tg_status_first_exp_bit | O | APP_DATA_WIDTH | If vio_tg_status_first_exp_bit_valid is set to 1, expected read data is stored in this register. |
| vio_tg_status_first_read_bit_valid | O | 1 | If vio_tg_err_chk_en is set to 1, this represents read data valid when first mismatch error is encountered. |
| vio_tg_status_first_read_bit | O | APP_DATA_WIDTH | If vio_tg_status_first_read_bit_valid is set to 1, read data from memory is stored in this register. |
| vio_tg_status_err_bit_sticky_valid | O | 1 | Accumulated error mismatch valid over time. This register is reset by vio_tg_err_clear, vio_tg_err_continue, vio_tg_restart. |
| vio_tg_status_err_bit_sticky | O | APP_DATA_WIDTH | If vio_tg_status_err_bit_sticky_valid is set to 1, this represents accumulated error bit. |
| vio_tg_status_err_type_valid | O | 1 | If vio_tg_err_chk_en is set to 1, read test is performed upon the first mismatch error. Read test returns error type of either "READ" or "WRITE" error. This register stores valid status of read test error type. |
| vio_tg_status_err_type | O | 1 | If vio_tg_status_err_type_valid
is set to 1, this represents error type result from read test.
|
| vio_tg_status_done | O | 1 | All traffic programmed
completes. Note: If infinite loop is programmed,
vio_tg_status_done does not assert.
|
| vio_tg_status_wr_done | O | 1 | This signal pulses after a WRITE-READ mode instruction completes. |
| vio_tg_status_watch_dog_hang | O | 1 | Watchdog hang. This register is set to 1 if there is no READ/WRITE command sent or no READ data return for a period of time (defined in tg_param.vh). |
| compare_error | O | 1 | Accumulated error mismatch valid over time. This register resets by vio_tg_err_clear, vio_tg_err_continue, vio_tg_restart. |