Timing Improvements for 3DS Designs - 1.0 English

The DDR4 3DS interfaces are not meeting timing for certain configurations. The failing timing paths are in the controller modules (u_ddr_mc instance). To meet timing for such cases, the Tcl command option is supported. Tcl command is supported for the Controller/PHY mode of Controller and Physical Layer and valid for 3DS parts only (S_HEIGHT parameter value of 2 or 4). Based on the Tcl command that is set in the console, a few RTL parameters are going to change which are listed in the following table.

DRAM pages are kept open as long as possible to reduce number of precharges. The controller contains a page table per bank and rank for each bank group. With 3DS, a third dimension is added to these page tables for logical ranks. This increases gate counts and makes timing closures harder. But the DRAM access performance is improved. ALIAS_PAGE = ON removes this dimension.

Similarly for 3DS, another dimension is added for logical rank to some per rank/bank counters which keeps track of tRAS, tRTP, and tWTP. ALIAS_P_CNT = ON removes the logical rank dimension.

Removing the third dimension does not affect correct operation of DRAM. However, it removes some of the performance advantages.

The default values of two parameters are given in the table. These parameters can be changed through the Tcl command using user parameter TIMING_3DS for Controller/PHY mode of Controller and Physical Layer. These Tcl options are not valid for any PHY_ONLY (Physical Layer Only and Physical Layer Ping Pong) designs.