Traffic Generator Structure - 1.0 English

In this section, the ATG logical structure and data flow is discussed.

The ATG data flow is summarized in the following figure. The ATG is controlled and programmed through the VIO interface. Based on current instruction pointer value, an instruction is issued by the ATG state machine.

Based on the traffic pattern programmed in Read/Write mode, Read and/or Write requests are sent to the application interface. Write patterns are generated by the Write Data Generation, Write Victim Pattern, and Write Address Generation engines (gray). Similarly, Read patterns are generated by Read Address Generation engine (dark gray).

When Write-Read-mode or Write-Once-Read-forever mode is programmed, Read data check is performed. Read data is compared against Expected Read pattern generated by the Expected Data Generation, Expected Victim Pattern, and Expected Address Generation engines (gray and white). Data compare is done in the Error Checker block. Error status is presented to the VIO interface.

The following figure and table show the ATG state machine and its states. The ATG resets at the "Start" state. After calibration completion (init_calib_complete) and the tg_start is asserted, the ATG state moves to instruction load called the "Load" state. The "Load" state performs next instruction load. When the instruction load is completed, the ATG state moves to Data initialization called the "Dinit" state. The "Dinit" state initializes all Data/Address generation engines. After completion of data initialization, the ATG state moves to execution called the "exe" state. The "Exe" state issues Read and/or Write requests to the application interface.

At the "Exe" state, you can pause the ATG and the ATG state moves to the "Pause" state. At the "Pause" state, the ATG can be restarted by issuing tg_restart through the VIO, or un-pause the ATG back to the "Exe" state

At the "Exe" state, the ATG state goes through RWWait > RWload > Dinit states if Write-Read mode or Write-once-Read-forever modes are used. At the RWload state, the ATG transitions from Write mode to Read mode for DDR4.

At the "Exe" state, the ATG state goes through LDWait > Load if the current instruction is completed. At the LDWait, the ATG waits for all Read requests to have data returned.

At the "Exe" state, the ATG state goes through DNWait > Done if the last instruction is completed. At the DNWait, the ATG waits for all Read requests to have data returned.

At the "Exe" state, the ATG state goes through ERRWait > ERRChk if an error is detected. At the ERRWait, the ATG waits for all Read requests to have data returned. The "ERRChk" state performs read test by issuing read requests to the application interface and determining whether "Read" or "Write" error occurred. After read test completion, the ATG state moves to "ERRDone".

At "Done," "Pause," and "ErrDone" states, the ATG can be restarted ATG by issuing tg_restart.