This register stores the decoded DRAM address (Bits[31:0]) of the first occurrence of an access with an uncorrectable error. The address format is defined in Error Address section. When the UE_STATUS bit in the ECC Status register is cleared, this register is re-enabled to store the address of the next uncorrectable error. Storing of the failing address is enabled after reset.
| Bits | Name | Core Access | Reset Value | Description |
|---|---|---|---|---|
| 31:0 | UE_FFA[31:0] | R | 0 | Address (Bits[31:0]) of the first occurrence of an uncorrectable error. |