Note: This register
is only used when the DQ_WIDTH == 144.
This register stores the (uncorrected) failing data (Bits[95:64]) of the first occurrence of an access with an uncorrectable error. When the UE_STATUS bit in the ECC Status register is cleared, this register is re-enabled to store the data of the next uncorrectable error. Storing of the failing data is enabled after reset.
Bits | Name | Core Access | Reset Value | Description |
---|---|---|---|---|
31:0 | UE_FFD[95:64] | R | 0 | Data (Bits[95:64]) of the first occurrence of an uncorrectable error. |