This register stores the ECC bits of the first occurrence of an access with an uncorrectable error. When the UE_STATUS bit in the ECC Status register is cleared, this register is re-enabled to store the ECC of the next uncorrectable error. Storing of the failing ECC is enabled after reset.
The table describes the register bit usage when DQ_WIDTH = 72.
Bits | Name | Core Access | Reset Value | Description |
---|---|---|---|---|
7:0 | UE_FFE | R | 0 | ECC (Bits[7:0]) of the first occurrence of an uncorrectable error. |
The table describes the register bit usage when DQ_WIDTH = 144.
Bits | Name | Core Access | Reset Value | Description |
---|---|---|---|---|
15:0 | UE_FFE | R | 0 | ECC (Bits[15:0]) of the first occurrence of an uncorrectable error. |