Usage - 1.0 English

Versal Adaptive SoC Soft DDR4 SDRAM Memory Controller LogiCORE IP Product Guide (PG353)
Document ID
PG353
Release Date
2023-10-18
Version
1.0 English

In this section, basic usage and programming of the ATG is covered.

The ATG is programmed and controlled using the VIO interface. Instruction table programming options are listed in the following table.

Table 1. Traffic Generator Instruction Options
Name Bit Width Description
Instruction Number 5 Instruction select. From 0 to 31.
Addr Mode 4

Address mode to be programmed.

0 = LINEAR; (with user-defined start address)

1 = PRBS; (PRBS supported range from 8 to 34 based on address width.)

2 = WALKING1

3 = WALKING0

4-15 = Reserved
Data Mode 4

Data mode to be programmed.

0 = LINEAR

1 = PRBS (PRBS supported 8, 10, 23)

2 = WALKING1

3 = WALKING0

4 = HAMMER1

5 = HAMMER0

6 = Block RAM

7 = CAL_CPLX

8-15 = Reserved
Read/Write Mode 4

0 = Read Only (No data check)

1 = Write Only (No data check)

2 = Write/Read (Read performs after Write and data value is checked against expected write data.)

3 = Write once and Read forever (Data check on Read data)

4-15 = Reserved
Read/Write Submode 2

Read/Write submode to be programmed.

This is a submode option when vio_tg_instr_rw_mode is set to "WRITE_READ" mode.

00 = WRITE_READ (Send all Write commands followed by Read commands defined in the instruction.)

01 = WRITE_READ_SIMULTANEOUSLY (Send Write and Read commands pseudo-randomly.)
Note: Write is always ahead of Read.

2 and 3 = Reserved
Victim Mode 3

Victim mode to be programmed.

One victim bit could be programmed using global register vio_tg_victim_bit. The rest of the bits on signal bus are considered to be aggressors.

The following program options define aggressor behavior:

0 = NO_VICTIM

1 = HELD1 (All aggressor signals held at 1.)

2 = HELD0 (All aggressor signals held at 0.)

3 = NONINV_AGGR (All aggressor signals are same as victim.)

4 = INV_AGGR (All aggressor signals are inversion of victim.)

5 = DELAYED_AGGR (All aggressor signals are delayed version of victim. Num of cycle of delay is programmed at vio_tg_victim_aggr_delay.)

6 = DELAYED_VICTIM (Victim signal is delayed version of all aggressors.)

7 = CAL_CPLX (Complex Calibration pattern)
Victim Aggressor Delay 5

Define aggressor/victim pattern to be N-delay cycle of victim/aggressor, where 0 ≤ N ≤ 24.

It is used when victim mode "DELAY_AGGR" or "DELAY VICTIM" mode is used in traffic pattern.
Victim Select 3

Victim bit behavior to be programmed.

0 = VICTIM_EXTERNAL (Use Victim bit provided in vio_tg_glb_victim_bit.)

1 = VICTIM_ROTATE4 (Victim bit rotates from Bits[3:0] for every Nibble.)

2 = VICTIM_ROTATE8 (Victim bit rotates from Bits[7:0] for every Byte.)

3 = VICTIM_ROTATE_ALL (Victim bit rotates through all bits.)

4-7 = RESERVED
Number of instruction iteration 32

Number of Read and/or Write commands to be sent.

N = APP_ADDR_WIDTH – 3
Note: APP_ADDR_WIDTH is defined in example_top.sv.

Linear Address Space Calculation: Max No. of iterations = 2N

PRBS Address Space Calculation: Max No. of iterations = 2N – 1

Walking1/0 Address Space Calculation: Max No. of iterations = N
Insert M NOPs between N-burst (M) 10 M = Number of NOP cycles in between Read/Write commands at user interface at general interconnect clock, where M ≥ 1.
Insert M NOPs between N-burst (N) 32 N = Number of Read/Write commands before NOP cycle insertion at user interface at general interconnect clock, where N ≥ 1.
Next Instruction 6

Next instruction to run.

To end traffic, next instruction should point at EXIT instruction.

6’b000000-6’b011111 – valid instruction

6’b1????? – EXIT instruction