User Interface - 1.0 English

Versal Adaptive SoC Soft DDR4 SDRAM Memory Controller LogiCORE IP Product Guide (PG353)

Document ID

PG353

Release Date

2023-10-18

Version

1.0 English

The user interface signals are connected to a Versal adaptive SoC user design to allow access to an external memory device. The user interface is layered on top of the native interface which is described earlier in the controller description.

Table 1. User Interface
Signal	I/O	Description
app_addr [APP_ADDR_WIDTH - 1:0]	I	This input indicates the address for the current request.
app_cmd[2:0]	I	This input selects the command for the current request.
app_autoprecharge¹	I	This input instructs the controller to set the A10 autoprecharge bit on the DRAM CAS command for the current request.
app_en	I	This is the active-High strobe for the app_addr[], app_cmd[2:0], and app_hi_pri inputs.
app_rdy	O	This output indicates that the user interface is ready to accept commands. If the signal is deasserted when app_en is enabled, the current app_cmd, app_autoprecharge, and app_addr must be retried until app_rdy is asserted.
app_hi_pri	I	This input is reserved and should be tied to 0.
app_rd_data [APP_DATA_WIDTH - 1:0]	O	This provides the output data from read commands.
app_rd_data_end	O	This active-High output indicates that the current clock cycle is the last cycle of output data on app_rd_data[].
app_rd_data_valid	O	This active-High output indicates that app_rd_data[] is valid.
app_wdf_data [APP_DATA_WIDTH - 1:0]	I	This provides the data for write commands.
app_wdf_end	I	This active-High input indicates that the current clock cycle is the last cycle of input data on app_wdf_data[].
app_wdf_mask [APP_MASK_WIDTH - 1:0]	I	This provides the mask for app_wdf_data[]. This input port appears in the "Data Mask and DBI" Vivado IDE option values of DM_NO_DBI and DM_DBI_RD.
app_wdf_rdy	O	This output indicates that the write data FIFO is ready to receive data. Write data is accepted when app_wdf_rdy = 1’b1 and app_wdf_wren = 1’b1.
app_wdf_wren	I	This is the active-High strobe for app_wdf_data[].
app_ref_req²	I	User refresh request.
app_ref_ack²	O	User refresh request completed.
app_zq_req²	I	User ZQCS command request.
app_zq_ack²	O	User ZQCS command request completed.
ui_clk	O	This user interface clock must be one quarter of the DRAM clock.
init_calib_complete	O	PHY asserts init_calib_complete when calibration is finished.
ui_clk_sync_rst	O	This is the active-High user interface reset.
dbg_clk	O	Debug Clock. Do not connect any signals to dbg_clk and keep the port open during instantiation.
sl_iport0	I [36:0]	Serial input port for debug interface.
sl_oport0	O [16:0]	Serial output port for debug interface.
ddr4_app_correct_en_i	I	When using the native interface with the input asserted, this enables ECC detection and correction.
LMB_UE	O	MCS Local Memory Uncorrectable Error (ECC only)
LMB_CE	O	MCS Local Memory Correctable Error (ECC only)
This port appears when "Enable Precharge Input" option is enabled in the Vivado IDE. These ports appear upon enabling "Enable User Refresh and ZQCS Input" option in the Vivado IDE.