The Memory Controller can be configured to automatically generate DRAM refresh and ZQCS maintenance commands to meet DRAM timing requirements. In this mode, the controller blocks the UI transactions on a regular basis to issue the maintenance commands, reducing efficiency.
If you have knowledge of the UI traffic pattern, you might be able to schedule
DRAM maintenance commands with less impact on system efficiency. You can use the
app_ref and app_zq ports at the UI to schedule
these commands when the controller is configured for User Refresh and ZQCS. In this
mode, the controller does not schedule the DRAM maintenance commands and only issues
them based on the app_ref and app_zq ports. You are
responsible for meeting all DRAM timing requirements for refresh and ZQCS.
Consider a case where the system needs to move a large amount of data into or out of the DRAM with the highest possible efficiency over a 50 µs period. If the controller schedules the maintenance commands, this 50 µs data burst would be interrupted multiple times for refresh, reducing efficiency roughly 4%. In User Refresh mode, however, you can decide to postpone refreshes during the 50 µs burst and make them up later. The DRAM specification allows up to eight refreshes to be postponed, giving you flexibility to schedule refreshes over a 9 × tREFI period, more than enough to cover the 50 µs in this example.
While User Refresh and ZQCS enable you to optimize efficiency, their incorrect
use can lead to DRAM timing violations and data loss in the DRAM. Use this mode only if
you thoroughly understand DRAM refresh and ZQCS requirements as well as the operation of
the app_ref and app_zq UI ports. The UI port operation
is described in the User Interface section.