Using VIO to Control ATG - 1.0 English

If you do not plan to program instruction table or PRBS data seed, tie this signal to 1'b1.

If you plan to program instruction table or PRBS data seed, set this bit to 0 during reset. After reset deassertion and done with instruction/seed programming, set this bit to 1 to start traffic generator.

If there is outstanding traffic in memory pipeline, assert this signal long enough until all outstanding transactions have completed.

If there is outstanding traffic in memory pipeline, assert this signal long enough until all outstanding transactions have completed.

Only use this signal when vio_tg_status_state is either TG_INSTR_ERRDONE or TG_INSTR_PAUSE. Error is cleared two cycles after vio_tg_err_clear is asserted.

Only use this signal when vio_tg_status_state is either TG_INSTR_ERRDONE or TG_INSTR_PAUSE. Error is cleared two cycles after vio_tg_err_clear is asserted.

1 = Direct Instruction Mode (Traffic Generator uses current traffic pattern presented at VIO interface.)

0 = LINEAR; (with user-defined start address)

1 = PRBS; (PRBS supported range from 8 to 34 based on address width.)

2 = WALKING1

3 = WALKING0

4-15 = Reserved

0 = LINEAR

1 = PRBS (PRBS supported 8, 10, 23)

2 = WALKING1

3 = WALKING0

4 = HAMMER1

5 = HAMMER0

6 = Block RAM

7 = CAL_CPLX X (Must be programmed along with victim mode CAL_CPLX)

8-15 = Reserved

1 = Write Only (No data check)

2 = Write/Read (Read performs after Write and data value is checked against expected write data.)

3 = Write once and Read forever (Data check on Read data)

4-15 = Reserved

This is a submode option when vio_tg_instr_rw_mode is set to "WRITE_READ" mode.

00 = WRITE_READ (Send all Write commands followed by Read commands defined in the instruction.)

2 and 3 = Reserved

One victim bit could be programmed using global register vio_tg_victim_bit. The rest of the bits on signal bus are considered to be aggressors.

The following program options define aggressor behavior:

0 = NO_VICTIM

1 = HELD1 (All aggressor signals held at 1.)

2 = HELD0 (All aggressor signals held at 0.)

3 = NONINV_AGGR (All aggressor signals are same as victim.)

4 = INV_AGGR (All aggressor signals are inversion of victim.)

5 = DELAYED_AGGR (All aggressor signals are delayed version of victim. Num of cycle of delay is programmed at vio_tg_victim_aggr_delay.)

6 = DELAYED_VICTIM (Victim signal is delayed version of all aggressors.)

7 = CAL_CPLX (Complex Calibration pattern must be programed along with Data Mode CAL_CPLX)

It is used when victim mode "DELAY_AGGR" or "DELAY VICTIM" mode is used in traffic pattern.

0 = VICTIM_EXTERNAL (Use Victim bit provided in vio_tg_glb_victim_bit.)

1 = VICTIM_ROTATE4 (Victim bit rotates from Bits[3:0] for every Nibble.)

2 = VICTIM_ROTATE8 (Victim bit rotates from Bits[7:0] for every Byte.)

3 = VICTIM_ROTATE_ALL (Victim bit rotates through all bits.)

4-7 = RESERVED

N: Number of Read/Write commands before NOP cycle insertion at User interface at general interconnect clock.

N: Number of Read/Write commands before NOP cycle insertion at User interface at general interconnect clock.

To end traffic, next instruction should point at EXIT instruction.

6’b000000-6’b011111 – valid instruction

6’b1????? – EXIT instruction

PRBS_DATA_WIDTH is by default 23. PRBS_DATA_WIDTH can support 8, 10, and 23.

The counter is reset by vio_tg_err_clear and vio_tg_err_clear_all.

This register is not overwritten until vio_tg_err_clear, vio_tg_err_continue, vio_tg_restart is triggered.

This register is reset by vio_tg_err_clear, vio_tg_err_continue, and vio_tg_restart.

The counter is reset by vio_tg_err_clear_all.

This register stores valid status of read test error type.

0 = Write Error

1 = Read Error

This register resets by vio_tg_err_clear, vio_tg_err_continue, and vio_tg_restart.