The DRAM requires the write DQS to be center-aligned with the DQ to ensure maximum write margin. The DQS and DQ ODELAY are used to fine tune the 90° phase alignment to ensure maximum margin at the DRAM.
A simple clock pattern of 10101010 is used initially because
the write latency has not yet been determined. Due to fly-by routing on the PCB/DIMM
module, the command to data timing is unknown until the next stage of calibration.
When issuing a write to the DRAM, the DQS and DQ toggles for four clock cycles
before and four clock cycles after the expected write latency. This is used to
ensure the data is written into the DRAM even if the command-to-write data
relationship is still unknown. Write calibration is divided into three phases.
- Write DQ Per-Bit Deskew
- Write DBI bit Deskew
- Write DQS to DQ/DBI Centering