XPHY BISC - 1.0 English

Versal Adaptive SoC Soft DDR4 SDRAM Memory Controller LogiCORE IP Product Guide (PG353)

Document ID
PG353
Release Date
2023-10-18
Version
1.0 English
After deassertion of the system reset, the built-in self-calibration (BISC) of the PHY is run. BISC is used in the PHY to compute internal skews for use in voltage and temperature tracking after calibration is completed. In this calibration stage, internal delays are measured to determine the number of fine taps required to equal a quarter clock memory period. This is referred to as a coarse tap.