XSDB Registers of Interest Write Leveling Calibration

XSDB Registers of Interest Write Leveling Calibration - 1.0 English

Versal Adaptive SoC Soft DDR4 SDRAM Memory Controller LogiCORE IP Product Guide (PG353)

Document ID

PG353

Release Date

2023-10-18

Version

1.0 English

The following table shows the XSDB registers and values adjusted or used during the Write Leveling stage of calibration. The values can be analyzed in both successful and failing calibrations to determine the resultant values and the consistency in results across resets. These values can be found within the Memory IP core properties in the Hardware Manager or by executing the Tcl commands noted in the Manually Analyzing the XSDB Output section.

Table 1. XSDB Registers of Interest Write Leveling Calibration
XSDB Reg	Usage	Signal Description
BRAM_WRLVL_CRSE_STG1 _RANK_BYTE	One value per rank per byte	WRLVL course tap setting to the last stable 0 seen just before the rising edge of CK.
BRAM_WRLVL_OFFSET_RANK_BYTE	One value per rank per byte	ODELAY Offset used during rising edge detection of CK.
BRAM_WRLVL_CRSE_FINAL_RANK_BYTE	One value per rank per byte	WRLVL course tap setting after confirming stable 0 just before the rising edge of CK.
BRAM_WRLVL_NOISE_FCRSE_RANK_BYTE	One value per rank per byte	WL_DLY_FINE tap value when left edge of noise is detected using step size of 10 taps.
BRAM_WRLVL_FINE_LEFT_RANK_BYTE	One value per rank per byte	WL_DLY_FINE tap value when left edge of noise is detected.
BRAM_WRLVL_FINE_RIGHT_RANK_BYTE	One value per rank per byte	WL_DLY_FINE tap value when right edge of noise is detected.
BRAM_WRLVL_FINE_FINAL_RANK_BYTE	One value per rank per byte	Final WL_DLY_FINE tap value. This is adjusted during alignment of DQS to CK.
BISC_ALIGN_PQTR_NIBBLE*	One per nibble	Initial 0° offset value provided by BISC at power-up.
BISC_ALIGN_NQTR_NIBBLE*	One per nibble	Initial 0° offset value provided by BISC at power-up.
BISC_PQTR_NIBBLE*	One per nibble	Initial 90° offset value provided by BISC at power-up. Compute 90° value in taps by taking (BISC_PQTR – BISC_ALIGN_PQTR). To estimate tap resolution take (¼ of the memory clock period)/ (BISC_PQTR – BISC_ALIGN_PQTR).
BISC_NQTR_NIBBLE*	One per nibble	Initial 90° offset value provided by BISC at power-up. Compute 90° value in taps by taking (BISC_PQTR – BISC_ALIGN_PQTR). To estimate tap resolution take (¼ of the memory clock period)/ (BISC_PQTR – BISC_ALIGN_PQTR).

This is a sample of the results for the Write Leveling XSDB debug signals:

BRAM_WRLVL_CRSE_STG1_RANK0_BYTE0              int     true       3
BRAM_WRLVL_CRSE_STG1_RANK0_BYTE1              int     true       3
BRAM_WRLVL_CRSE_STG1_RANK0_BYTE2              int     true       0
BRAM_WRLVL_CRSE_STG1_RANK0_BYTE3              int     true       3
BRAM_WRLVL_CRSE_STG1_RANK0_BYTE4              int     true       0
BRAM_WRLVL_CRSE_STG1_RANK0_BYTE5              int     true       1
BRAM_WRLVL_CRSE_STG1_RANK0_BYTE6              int     true       1
BRAM_WRLVL_CRSE_STG1_RANK0_BYTE7              int     true       1
BRAM_WRLVL_OFFSET_RANK0_BYTE0                 int     true       0
BRAM_WRLVL_OFFSET_RANK0_BYTE1                 int     true       0
BRAM_WRLVL_OFFSET_RANK0_BYTE2                 int     true       0
BRAM_WRLVL_OFFSET_RANK0_BYTE3                 int     true       0
BRAM_WRLVL_OFFSET_RANK0_BYTE4                 int     true       0
BRAM_WRLVL_OFFSET_RANK0_BYTE5                 int     true       0
BRAM_WRLVL_OFFSET_RANK0_BYTE6                 int     true       0
BRAM_WRLVL_OFFSET_RANK0_BYTE7                 int     true       0
BRAM_WRLVL_CRSE_FINAL_RANK0_BYTE0             int     true       3
BRAM_WRLVL_CRSE_FINAL_RANK0_BYTE1             int     true       3
BRAM_WRLVL_CRSE_FINAL_RANK0_BYTE2             int     true       3
BRAM_WRLVL_CRSE_FINAL_RANK0_BYTE3             int     true       2
BRAM_WRLVL_CRSE_FINAL_RANK0_BYTE4             int     true       0
BRAM_WRLVL_CRSE_FINAL_RANK0_BYTE5             int     true       1
BRAM_WRLVL_CRSE_FINAL_RANK0_BYTE6             int     true       1
BRAM_WRLVL_CRSE_FINAL_RANK0_BYTE7             int     true       1
BRAM_WRLVL_NOISE_FCRSE_RANK0_BYTE0            int     true       0
BRAM_WRLVL_NOISE_FCRSE_RANK0_BYTE1            int     true       0
BRAM_WRLVL_NOISE_FCRSE_RANK0_BYTE2            int     true       0
BRAM_WRLVL_NOISE_FCRSE_RANK0_BYTE3            int     true       0
BRAM_WRLVL_NOISE_FCRSE_RANK0_BYTE4            int     true       0
BRAM_WRLVL_NOISE_FCRSE_RANK0_BYTE5            int     true       0
BRAM_WRLVL_NOISE_FCRSE_RANK0_BYTE6            int     true       0
BRAM_WRLVL_NOISE_FCRSE_RANK0_BYTE7            int     true       0
BRAM_WRLVL_FINE_LEFT_RANK0_BYTE0              int     true       7
BRAM_WRLVL_FINE_LEFT_RANK0_BYTE1              int     true       9
BRAM_WRLVL_FINE_LEFT_RANK0_BYTE2              int     true       0
BRAM_WRLVL_FINE_LEFT_RANK0_BYTE3              int     true       4
BRAM_WRLVL_FINE_LEFT_RANK0_BYTE4              int     true       4
BRAM_WRLVL_FINE_LEFT_RANK0_BYTE5              int     true       4
BRAM_WRLVL_FINE_LEFT_RANK0_BYTE6              int     true       1
BRAM_WRLVL_FINE_LEFT_RANK0_BYTE7              int     true       5
BRAM_WRLVL_FINE_RIGHT_RANK0_BYTE0             int     true       22
BRAM_WRLVL_FINE_RIGHT_RANK0_BYTE1             int     true       24
BRAM_WRLVL_FINE_RIGHT_RANK0_BYTE2             int     true       17
BRAM_WRLVL_FINE_RIGHT_RANK0_BYTE3             int     true       9
BRAM_WRLVL_FINE_RIGHT_RANK0_BYTE4             int     true       21
BRAM_WRLVL_FINE_RIGHT_RANK0_BYTE5             int     true       19
BRAM_WRLVL_FINE_RIGHT_RANK0_BYTE6             int     true       17
BRAM_WRLVL_FINE_RIGHT_RANK0_BYTE7             int     true       21
BRAM_WRLVL_FINE_FINAL_RANK0_BYTE0             int     true       31
BRAM_WRLVL_FINE_FINAL_RANK0_BYTE1             int     true       63
BRAM_WRLVL_FINE_FINAL_RANK0_BYTE2             int     true       105
BRAM_WRLVL_FINE_FINAL_RANK0_BYTE3             int     true       93
BRAM_WRLVL_FINE_FINAL_RANK0_BYTE4             int     true       59
BRAM_WRLVL_FINE_FINAL_RANK0_BYTE5             int     true       28
BRAM_WRLVL_FINE_FINAL_RANK0_BYTE6             int     true       55
BRAM_WRLVL_FINE_FINAL_RANK0_BYTE7             int     true       99
BRAM_BISC_PQTR_ALIGN_NIBBLE0                  int     true       1
BRAM_BISC_PQTR_ALIGN_NIBBLE1                  int     true       0
BRAM_BISC_PQTR_ALIGN_NIBBLE2                  int     true       1
BRAM_BISC_PQTR_ALIGN_NIBBLE3                  int     true       0
BRAM_BISC_PQTR_ALIGN_NIBBLE4                  int     true       0
BRAM_BISC_PQTR_ALIGN_NIBBLE5                  int     true       2
BRAM_BISC_PQTR_ALIGN_NIBBLE6                  int     true       0
BRAM_BISC_PQTR_ALIGN_NIBBLE7                  int     true       0
BRAM_BISC_PQTR_ALIGN_NIBBLE8                  int     true       1
BRAM_BISC_PQTR_ALIGN_NIBBLE9                  int     true       1
BRAM_BISC_PQTR_ALIGN_NIBBLE10                 int     true       0
BRAM_BISC_PQTR_ALIGN_NIBBLE11                 int     true       33
BRAM_BISC_PQTR_ALIGN_NIBBLE12                 int     true       0
BRAM_BISC_PQTR_ALIGN_NIBBLE13                 int     true       1
BRAM_BISC_PQTR_ALIGN_NIBBLE14                 int     true       1
BRAM_BISC_PQTR_ALIGN_NIBBLE15                 int     true       2
BRAM_BISC_NQTR_ALIGN_NIBBLE0                  int     true       0
BRAM_BISC_NQTR_ALIGN_NIBBLE1                  int     true       1
BRAM_BISC_NQTR_ALIGN_NIBBLE2                  int     true       0
BRAM_BISC_NQTR_ALIGN_NIBBLE3                  int     true       1
BRAM_BISC_NQTR_ALIGN_NIBBLE4                  int     true       0
BRAM_BISC_NQTR_ALIGN_NIBBLE5                  int     true       0
BRAM_BISC_NQTR_ALIGN_NIBBLE6                  int     true       2
BRAM_BISC_NQTR_ALIGN_NIBBLE7                  int     true       0
BRAM_BISC_NQTR_ALIGN_NIBBLE8                  int     true       0
BRAM_BISC_NQTR_ALIGN_NIBBLE9                  int     true       0
BRAM_BISC_NQTR_ALIGN_NIBBLE10                 int     true       1
BRAM_BISC_NQTR_ALIGN_NIBBLE11                 int     true       0
BRAM_BISC_NQTR_ALIGN_NIBBLE12                 int     true       1
BRAM_BISC_NQTR_ALIGN_NIBBLE13                 int     true       0
BRAM_BISC_NQTR_ALIGN_NIBBLE14                 int     true       0
BRAM_BISC_NQTR_ALIGN_NIBBLE15                 int     true       0
BRAM_BISC_PQTR_NIBBLE0                        int     true       89
BRAM_BISC_PQTR_NIBBLE1                        int     true       88
BRAM_BISC_PQTR_NIBBLE2                        int     true       89
BRAM_BISC_PQTR_NIBBLE3                        int     true       87
BRAM_BISC_PQTR_NIBBLE4                        int     true       88
BRAM_BISC_PQTR_NIBBLE5                        int     true       88
BRAM_BISC_PQTR_NIBBLE6                        int     true       89
BRAM_BISC_PQTR_NIBBLE7                        int     true       88
BRAM_BISC_PQTR_NIBBLE8                        int     true       88
BRAM_BISC_PQTR_NIBBLE9                        int     true       91
BRAM_BISC_PQTR_NIBBLE10                       int     true       90
BRAM_BISC_PQTR_NIBBLE11                       int     true       92
BRAM_BISC_PQTR_NIBBLE12                       int     true       89
BRAM_BISC_PQTR_NIBBLE13                       int     true       90
BRAM_BISC_PQTR_NIBBLE14                       int     true       90
BRAM_BISC_PQTR_NIBBLE15                       int     true       90
BRAM_BISC_NQTR_NIBBLE0                        int     true       87
BRAM_BISC_NQTR_NIBBLE1                        int     true       90
BRAM_BISC_NQTR_NIBBLE2                        int     true       90
BRAM_BISC_NQTR_NIBBLE3                        int     true       89
BRAM_BISC_NQTR_NIBBLE4                        int     true       87
BRAM_BISC_NQTR_NIBBLE5                        int     true       89
BRAM_BISC_NQTR_NIBBLE6                        int     true       91
BRAM_BISC_NQTR_NIBBLE7                        int     true       91
BRAM_BISC_NQTR_NIBBLE8                        int     true       87
BRAM_BISC_NQTR_NIBBLE9                        int     true       91
BRAM_BISC_NQTR_NIBBLE10                       int     true       90
BRAM_BISC_NQTR_NIBBLE11                       int     true       91
BRAM_BISC_NQTR_NIBBLE12                       int     true       90
BRAM_BISC_NQTR_NIBBLE13                       int     true       90
BRAM_BISC_NQTR_NIBBLE14                       int     true       88
BRAM_BISC_NQTR_NIBBLE15                       int     true       89