The following table shows the XSDB registers and values adjusted or used during the DQS Preamble Detection stage of calibration. The values can be analyzed in both successful and failing calibrations to determine the resultant values and the consistency in results across resets. These values can be found within the Memory IP core properties in the Hardware Manager or by executing the Tcl commands noted in the Manually Analyzing the XSDB Output section.
| XSDB Reg | Usage | Signal Description |
|---|---|---|
| BRAM_DQSGATE_STG1_OVERFLOW_* | One value per rank and DQS group | Coarse tap overflow status during XPHY based DQS gate calibration. |
| BRAM_DQSGATE_STG1_READ_LAT_RANK*_BYTE* | One value per rank and DQS group | Read Latency value after centering the internal clock to the noise region of third edge of DQS strobe. |
| BRAM_DQSGATE_STG1_RLDLYRNK_CRSE_RANK*_BYTE* | One value per rank and DQS group | Coarse tap value after centering the internal clock to the noise region of third edge of DQS strobe. |
| BRAM_DQSGATE_STG1_RLDLYRNK_FINE_RANK*_BYTE* | One value per rank and DQS group | Fine tap value after centering the internal clock to the noise region of third edge of DQS strobe. |
| BRAM_DQSGATE_STG2_READ_LAT_RANK*_BYTE* | One value per rank and DQS group | Read Latency value after adjusting coarse tap value in range of 6 to 9. |
| BRAM_DQSGATE_STG2_RLDLYRNK_CRSE_RANK*_BYTE* | One value per rank and DQS group | Coarse tap value after adjusting coarse tap value in range of 6 to 9. |
| BRAM_DQSGATE_MAX_READ_LAT | Only one value | Maximum Read Latency across all rank just before the start of multi-rank adjustment. |
| BRAM_DQSGATE_READ_LAT_FINAL_BYTE* | One value per DQS group | Read Latency final value after multi-rank adjustment. The Read Latency field is limited to CAS latency -3 to CAS latency + 7. If the DQS is toggling yet was not found check the latency of the DQS signal coming back in relation to the chip select. |
| BRAM_DQSGATE_RLDLYRNK_CRSE_FINAL_RANK*_BYTE* | One value per rank and DQS group | Coarse tap final value after multi-rank adjustment. |
| BISC_ALIGN_PQTR_NIBBLE* | One per nibble | Initial 0° offset value provided by BISC at power-up. |
| BISC_ALIGN_NQTR_NIBBLE* | One per nibble | Initial 0° offset value provided by BISC at power-up. |
| BISC_PQTR_NIBBLE* | One per nibble | Initial 90° offset value provided by BISC at power-up. Compute 90° value in taps by taking (BISC_PQTR – BISC_ALIGN_PQTR). To estimate tap resolution take (¼ of the memory clock period)/ (BISC_PQTR – BISC_ALIGN_PQTR). |
| BISC_NQTR_NIBBLE* | One per nibble | Initial 90° offset value provided by BISC at power-up. Compute 90° value in taps by taking (BISC_PQTR – BISC_ALIGN_PQTR). To estimate tap resolution take (¼ of the memory clock period)/ (BISC_PQTR – BISC_ALIGN_PQTR). |
This is a sample of the results for the DQS Preamble Detection XSDB debug signals:
BRAM_DQSGATE_STG1_OVERFLOW_00 int true 0
BRAM_DQSGATE_STG1_OVERFLOW_01 int true 0
BRAM_DQSGATE_STG1_OVERFLOW_02 int true 0
BRAM_DQSGATE_STG1_OVERFLOW_03 int true 0
BRAM_DQSGATE_STG1_OVERFLOW_04 int true 0
BRAM_DQSGATE_STG1_OVERFLOW_05 int true 0
BRAM_DQSGATE_STG1_OVERFLOW_06 int true 0
BRAM_DQSGATE_STG1_OVERFLOW_07 int true 0
BRAM_DQSGATE_STG1_OVERFLOW_08 int true 0
BRAM_DQSGATE_STG1_OVERFLOW_09 int true 0
BRAM_DQSGATE_STG1_OVERFLOW_10 int true 0
BRAM_DQSGATE_STG1_OVERFLOW_11 int true 0
BRAM_DQSGATE_STG1_OVERFLOW_12 int true 0
BRAM_DQSGATE_STG1_OVERFLOW_13 int true 0
BRAM_DQSGATE_STG1_OVERFLOW_14 int true 0
BRAM_DQSGATE_STG1_OVERFLOW_15 int true 0
BRAM_DQSGATE_STG1_OVERFLOW_16 int true 0
BRAM_DQSGATE_STG1_OVERFLOW_17 int true 0
BRAM_DQSGATE_STG1_OVERFLOW_18 int true 0
BRAM_DQSGATE_STG1_OVERFLOW_19 int true 0
BRAM_DQSGATE_STG1_OVERFLOW_20 int true 0
BRAM_DQSGATE_STG1_OVERFLOW_21 int true 0
BRAM_DQSGATE_STG1_OVERFLOW_22 int true 0
BRAM_DQSGATE_STG1_OVERFLOW_23 int true 0
BRAM_DQSGATE_STG1_OVERFLOW_24 int true 0
BRAM_DQSGATE_STG1_OVERFLOW_25 int true 0
BRAM_DQSGATE_STG1_OVERFLOW_26 int true 0
BRAM_DQSGATE_STG1_OVERFLOW_27 int true 0
BRAM_DQSGATE_STG1_OVERFLOW_28 int true 0
BRAM_DQSGATE_STG1_OVERFLOW_29 int true 0
BRAM_DQSGATE_STG1_OVERFLOW_30 int true 0
BRAM_DQSGATE_STG1_OVERFLOW_31 int true 0
BRAM_DQSGATE_STG1_OVERFLOW_32 int true 0
BRAM_DQSGATE_STG1_OVERFLOW_33 int true 0
BRAM_DQSGATE_STG1_OVERFLOW_34 int true 0
BRAM_DQSGATE_STG1_OVERFLOW_35 int true 0
BRAM_DQSGATE_STG1_OVERFLOW_36 int true 0
BRAM_DQSGATE_STG1_OVERFLOW_37 int true 0
BRAM_DQSGATE_STG1_OVERFLOW_38 int true 0
BRAM_DQSGATE_STG1_OVERFLOW_39 int true 0
BRAM_DQSGATE_STG1_OVERFLOW_40 int true 0
BRAM_DQSGATE_STG1_OVERFLOW_41 int true 0
BRAM_DQSGATE_STG1_OVERFLOW_42 int true 0
BRAM_DQSGATE_STG1_OVERFLOW_43 int true 0
BRAM_DQSGATE_STG1_OVERFLOW_44 int true 0
BRAM_DQSGATE_STG1_OVERFLOW_45 int true 0
BRAM_DQSGATE_STG1_OVERFLOW_46 int true 0
BRAM_DQSGATE_STG1_OVERFLOW_47 int true 0
BRAM_DQSGATE_STG1_OVERFLOW_48 int true 0
BRAM_DQSGATE_STG1_OVERFLOW_49 int true 0
BRAM_DQSGATE_STG1_OVERFLOW_50 int true 0
BRAM_DQSGATE_STG1_OVERFLOW_51 int true 0
BRAM_DQSGATE_STG1_OVERFLOW_52 int true 0
BRAM_DQSGATE_STG1_OVERFLOW_53 int true 0
BRAM_DQSGATE_STG1_OVERFLOW_54 int true 0
BRAM_DQSGATE_STG1_OVERFLOW_55 int true 0
BRAM_DQSGATE_STG1_OVERFLOW_56 int true 0
BRAM_DQSGATE_STG1_OVERFLOW_57 int true 0
BRAM_DQSGATE_STG1_OVERFLOW_58 int true 0
BRAM_DQSGATE_STG1_OVERFLOW_59 int true 0
BRAM_DQSGATE_STG1_OVERFLOW_60 int true 0
BRAM_DQSGATE_STG1_OVERFLOW_61 int true 0
BRAM_DQSGATE_STG1_OVERFLOW_62 int true 0
BRAM_DQSGATE_STG1_OVERFLOW_63 int true 0
BRAM_DQSGATE_STG1_OVERFLOW_64 int true 0
BRAM_DQSGATE_STG1_OVERFLOW_65 int true 0
BRAM_DQSGATE_STG1_OVERFLOW_66 int true 0
BRAM_DQSGATE_STG1_OVERFLOW_67 int true 0
BRAM_DQSGATE_STG1_OVERFLOW_68 int true 0
BRAM_DQSGATE_STG1_OVERFLOW_69 int true 0
BRAM_DQSGATE_STG1_OVERFLOW_70 int true 0
BRAM_DQSGATE_STG1_OVERFLOW_71 int true 0
BRAM_DQSGATE_STG1_OVERFLOW_72 int true 0
BRAM_DQSGATE_STG1_OVERFLOW_73 int true 0
BRAM_DQSGATE_STG1_OVERFLOW_74 int true 0
BRAM_DQSGATE_STG1_OVERFLOW_75 int true 0
BRAM_DQSGATE_STG1_OVERFLOW_76 int true 0
BRAM_DQSGATE_STG1_OVERFLOW_77 int true 0
BRAM_DQSGATE_STG1_OVERFLOW_78 int true 0
BRAM_DQSGATE_STG1_OVERFLOW_79 int true 0
BRAM_DQSGATE_STG1_OVERFLOW_80 int true 0
BRAM_DQSGATE_STG1_OVERFLOW_81 int true 0
BRAM_DQSGATE_STG1_OVERFLOW_82 int true 0
BRAM_DQSGATE_STG1_OVERFLOW_83 int true 0
BRAM_DQSGATE_STG1_OVERFLOW_84 int true 0
BRAM_DQSGATE_STG1_OVERFLOW_85 int true 0
BRAM_DQSGATE_STG1_OVERFLOW_86 int true 0
BRAM_DQSGATE_STG1_OVERFLOW_87 int true 0
BRAM_DQSGATE_STG1_OVERFLOW_88 int true 0
BRAM_DQSGATE_STG1_OVERFLOW_89 int true 0
BRAM_DQSGATE_STG1_OVERFLOW_90 int true 0
BRAM_DQSGATE_STG1_OVERFLOW_91 int true 0
BRAM_DQSGATE_STG1_OVERFLOW_92 int true 0
BRAM_DQSGATE_STG1_OVERFLOW_93 int true 0
BRAM_DQSGATE_STG1_OVERFLOW_94 int true 0
BRAM_DQSGATE_STG1_OVERFLOW_95 int true 0
BRAM_DQSGATE_STG1_READ_LAT_RANK0_BYTE0 int true 24
BRAM_DQSGATE_STG1_READ_LAT_RANK0_BYTE1 int true 24
BRAM_DQSGATE_STG1_READ_LAT_RANK0_BYTE2 int true 24
BRAM_DQSGATE_STG1_READ_LAT_RANK0_BYTE3 int true 24
BRAM_DQSGATE_STG1_READ_LAT_RANK0_BYTE4 int true 24
BRAM_DQSGATE_STG1_READ_LAT_RANK0_BYTE5 int true 24
BRAM_DQSGATE_STG1_READ_LAT_RANK0_BYTE6 int true 27
BRAM_DQSGATE_STG1_READ_LAT_RANK0_BYTE7 int true 27
BRAM_DQSGATE_STG1_RLDLYRNK_CRSE_RANK0_BYTE0 int true 11
BRAM_DQSGATE_STG1_RLDLYRNK_CRSE_RANK0_BYTE1 int true 12
BRAM_DQSGATE_STG1_RLDLYRNK_CRSE_RANK0_BYTE2 int true 13
BRAM_DQSGATE_STG1_RLDLYRNK_CRSE_RANK0_BYTE3 int true 14
BRAM_DQSGATE_STG1_RLDLYRNK_CRSE_RANK0_BYTE4 int true 15
BRAM_DQSGATE_STG1_RLDLYRNK_CRSE_RANK0_BYTE5 int true 15
BRAM_DQSGATE_STG1_RLDLYRNK_CRSE_RANK0_BYTE6 int true 4
BRAM_DQSGATE_STG1_RLDLYRNK_CRSE_RANK0_BYTE7 int true 5
BRAM_DQSGATE_STG1_RLDLYRNK_FINE_RANK0_BYTE0 int true 71
BRAM_DQSGATE_STG1_RLDLYRNK_FINE_RANK0_BYTE1 int true 68
BRAM_DQSGATE_STG1_RLDLYRNK_FINE_RANK0_BYTE2 int true 25
BRAM_DQSGATE_STG1_RLDLYRNK_FINE_RANK0_BYTE3 int true 68
BRAM_DQSGATE_STG1_RLDLYRNK_FINE_RANK0_BYTE4 int true 0
BRAM_DQSGATE_STG1_RLDLYRNK_FINE_RANK0_BYTE5 int true 13
BRAM_DQSGATE_STG1_RLDLYRNK_FINE_RANK0_BYTE6 int true 41
BRAM_DQSGATE_STG1_RLDLYRNK_FINE_RANK0_BYTE7 int true 20
BRAM_DQSGATE_STG2_READ_LAT_RANK0_BYTE0 int true 25
BRAM_DQSGATE_STG2_READ_LAT_RANK0_BYTE1 int true 25
BRAM_DQSGATE_STG2_READ_LAT_RANK0_BYTE2 int true 25
BRAM_DQSGATE_STG2_READ_LAT_RANK0_BYTE3 int true 26
BRAM_DQSGATE_STG2_READ_LAT_RANK0_BYTE4 int true 26
BRAM_DQSGATE_STG2_READ_LAT_RANK0_BYTE5 int true 26
BRAM_DQSGATE_STG2_READ_LAT_RANK0_BYTE6 int true 26
BRAM_DQSGATE_STG2_READ_LAT_RANK0_BYTE7 int true 26
BRAM_DQSGATE_STG2_RLDLYRNK_CRSE_RANK0_BYTE0 int true 7
BRAM_DQSGATE_STG2_RLDLYRNK_CRSE_RANK0_BYTE1 int true 8
BRAM_DQSGATE_STG2_RLDLYRNK_CRSE_RANK0_BYTE2 int true 9
BRAM_DQSGATE_STG2_RLDLYRNK_CRSE_RANK0_BYTE3 int true 6
BRAM_DQSGATE_STG2_RLDLYRNK_CRSE_RANK0_BYTE4 int true 7
BRAM_DQSGATE_STG2_RLDLYRNK_CRSE_RANK0_BYTE5 int true 7
BRAM_DQSGATE_STG2_RLDLYRNK_CRSE_RANK0_BYTE6 int true 8
BRAM_DQSGATE_STG2_RLDLYRNK_CRSE_RANK0_BYTE7 int true 9
BRAM_DQSGATE_MAX_READ_LAT int true 26
BRAM_DQSGATE_READ_LAT_FINAL_BYTE0 int true 25
BRAM_DQSGATE_READ_LAT_FINAL_BYTE1 int true 25
BRAM_DQSGATE_READ_LAT_FINAL_BYTE2 int true 25
BRAM_DQSGATE_READ_LAT_FINAL_BYTE3 int true 26
BRAM_DQSGATE_READ_LAT_FINAL_BYTE4 int true 26
BRAM_DQSGATE_READ_LAT_FINAL_BYTE5 int true 26
BRAM_DQSGATE_READ_LAT_FINAL_BYTE6 int true 26
BRAM_DQSGATE_READ_LAT_FINAL_BYTE7 int true 26
BRAM_DQSGATE_RLDLYRNK_CRSE_FINAL_RANK0_BYTE0 int true 7
BRAM_DQSGATE_RLDLYRNK_CRSE_FINAL_RANK0_BYTE1 int true 8
BRAM_DQSGATE_RLDLYRNK_CRSE_FINAL_RANK0_BYTE2 int true 9
BRAM_DQSGATE_RLDLYRNK_CRSE_FINAL_RANK0_BYTE3 int true 6
BRAM_DQSGATE_RLDLYRNK_CRSE_FINAL_RANK0_BYTE4 int true 7
BRAM_DQSGATE_RLDLYRNK_CRSE_FINAL_RANK0_BYTE5 int true 7
BRAM_DQSGATE_RLDLYRNK_CRSE_FINAL_RANK0_BYTE6 int true 8
BRAM_DQSGATE_RLDLYRNK_CRSE_FINAL_RANK0_BYTE7 int true 9
BRAM_BISC_PQTR_ALIGN_NIBBLE0 int true 1
BRAM_BISC_PQTR_ALIGN_NIBBLE1 int true 0
BRAM_BISC_PQTR_ALIGN_NIBBLE2 int true 1
BRAM_BISC_PQTR_ALIGN_NIBBLE3 int true 0
BRAM_BISC_PQTR_ALIGN_NIBBLE4 int true 0
BRAM_BISC_PQTR_ALIGN_NIBBLE5 int true 2
BRAM_BISC_PQTR_ALIGN_NIBBLE6 int true 0
BRAM_BISC_PQTR_ALIGN_NIBBLE7 int true 0
BRAM_BISC_PQTR_ALIGN_NIBBLE8 int true 1
BRAM_BISC_PQTR_ALIGN_NIBBLE9 int true 1
BRAM_BISC_PQTR_ALIGN_NIBBLE10 int true 0
BRAM_BISC_PQTR_ALIGN_NIBBLE11 int true 33
BRAM_BISC_PQTR_ALIGN_NIBBLE12 int true 0
BRAM_BISC_PQTR_ALIGN_NIBBLE13 int true 1
BRAM_BISC_PQTR_ALIGN_NIBBLE14 int true 1
BRAM_BISC_PQTR_ALIGN_NIBBLE15 int true 2
BRAM_BISC_NQTR_ALIGN_NIBBLE0 int true 0
BRAM_BISC_NQTR_ALIGN_NIBBLE1 int true 1
BRAM_BISC_NQTR_ALIGN_NIBBLE2 int true 0
BRAM_BISC_NQTR_ALIGN_NIBBLE3 int true 1
BRAM_BISC_NQTR_ALIGN_NIBBLE4 int true 0
BRAM_BISC_NQTR_ALIGN_NIBBLE5 int true 0
BRAM_BISC_NQTR_ALIGN_NIBBLE6 int true 2
BRAM_BISC_NQTR_ALIGN_NIBBLE7 int true 0
BRAM_BISC_NQTR_ALIGN_NIBBLE8 int true 0
BRAM_BISC_NQTR_ALIGN_NIBBLE9 int true 0
BRAM_BISC_NQTR_ALIGN_NIBBLE10 int true 1
BRAM_BISC_NQTR_ALIGN_NIBBLE11 int true 0
BRAM_BISC_NQTR_ALIGN_NIBBLE12 int true 1
BRAM_BISC_NQTR_ALIGN_NIBBLE13 int true 0
BRAM_BISC_NQTR_ALIGN_NIBBLE14 int true 0
BRAM_BISC_NQTR_ALIGN_NIBBLE15 int true 0
BRAM_BISC_PQTR_NIBBLE0 int true 89
BRAM_BISC_PQTR_NIBBLE1 int true 88
BRAM_BISC_PQTR_NIBBLE2 int true 89
BRAM_BISC_PQTR_NIBBLE3 int true 87
BRAM_BISC_PQTR_NIBBLE4 int true 88
BRAM_BISC_PQTR_NIBBLE5 int true 88
BRAM_BISC_PQTR_NIBBLE6 int true 89
BRAM_BISC_PQTR_NIBBLE7 int true 88
BRAM_BISC_PQTR_NIBBLE8 int true 88
BRAM_BISC_PQTR_NIBBLE9 int true 91
BRAM_BISC_PQTR_NIBBLE10 int true 90
BRAM_BISC_PQTR_NIBBLE11 int true 92
BRAM_BISC_PQTR_NIBBLE12 int true 89
BRAM_BISC_PQTR_NIBBLE13 int true 90
BRAM_BISC_PQTR_NIBBLE14 int true 90
BRAM_BISC_PQTR_NIBBLE15 int true 90
BRAM_BISC_NQTR_NIBBLE0 int true 87
BRAM_BISC_NQTR_NIBBLE1 int true 90
BRAM_BISC_NQTR_NIBBLE2 int true 90
BRAM_BISC_NQTR_NIBBLE3 int true 89
BRAM_BISC_NQTR_NIBBLE4 int true 87
BRAM_BISC_NQTR_NIBBLE5 int true 89
BRAM_BISC_NQTR_NIBBLE6 int true 91
BRAM_BISC_NQTR_NIBBLE7 int true 91
BRAM_BISC_NQTR_NIBBLE8 int true 87
BRAM_BISC_NQTR_NIBBLE9 int true 91
BRAM_BISC_NQTR_NIBBLE10 int true 90
BRAM_BISC_NQTR_NIBBLE11 int true 91
BRAM_BISC_NQTR_NIBBLE12 int true 90
BRAM_BISC_NQTR_NIBBLE13 int true 90
BRAM_BISC_NQTR_NIBBLE14 int true 88
BRAM_BISC_NQTR_NIBBLE15 int true 89