The table shows the XSDB registers and values adjusted or used during the Read DQS Centering stage of calibration. The values can be analyzed in both successful and failing calibrations to determine the resultant values and the consistency in results across resets. These values can be found within the Memory IP core properties in the Hardware Manager or by executing the Tcl commands noted in the Manually Analyzing the XSDB Output section.
| XSDB Reg | Usage | Signal Description |
|---|---|---|
| BRAM_RDDQ_IDELAY_FINAL_BIT* | One per bit | Read leveling IDELAY delay value found during Read DQS Centering. |
| BRAM_RDDQ_PQTR_LEFT_NIBBLE* | One per nibble | Read leveling PQTR tap position when left edge of read data valid window is detected (Simple). |
| BRAM_RDDQ_NQTR_LEFT_NIBBLE* | One per nibble | Read leveling NQTR tap position when left edge of read data valid window is detected (Simple). |
| BRAM_RDDQ_PQTR_RIGHT_FCRSE_NIBBLE* | One per nibble | Read leveling PQTR tap position when right edge of read data valid window is detected by incrementing PQTR/NQTR IDELAY using step size of 10 taps (Simple). |
| BRAM_RDDQ_NQTR_RIGHT_FCRSE_NIBBLE* | One per nibble | Read leveling NQTR tap position when right edge of read data valid window is detected by incrementing PQTR/NQTR IDELAY using step size of 10 taps (Simple). |
| BRAM_RDDQ_PQTR_RIGHT_NIBBLE* | One per nibble | Read leveling PQTR tap position when right edge of read data valid window is detected (Simple). |
| BRAM_RDDQ_NQTR_RIGHT_NIBBLE* | One per nibble | Read leveling NQTR tap position when right edge of read data valid window is detected (Simple). |
| BRAM_RDDQ_PQTR_FINAL_NIBBLE* | One per nibble | Read leveling PQTR center tap position found at the end of read DQS centering (Simple). |
| BRAM_RDDQ_NQTR_FINAL_NIBBLE* | One per nibble | Read leveling NQTR center tap position found at the end of read DQS centering (Simple). |
| BISC_ALIGN_PQTR_NIBBLE* | One per nibble | Initial 0° offset value provided by BISC at power-up. |
| BISC_ALIGN_NQTR_NIBBLE* | One per nibble | Initial 0° offset value provided by BISC at power-up. |
| BISC_PQTR_NIBBLE* | One per nibble | Initial 90° offset value provided by BISC at power-up. Compute 90° value in taps by taking (BISC_PQTR – BISC_ALIGN_PQTR). To estimate tap resolution take (¼ of the memory clock period)/ (BISC_PQTR – BISC_ALIGN_PQTR). |
| BISC_NQTR_NIBBLE* | One per nibble | Initial 90° offset value provided by BISC at power-up. Compute 90° value in taps by taking (BISC_PQTR – BISC_ALIGN_PQTR). To estimate tap resolution take (¼ of the memory clock period)/ (BISC_PQTR – BISC_ALIGN_PQTR). |
This is a sample of results for Read MPR DQS Centering using the Memory IP Debug GUI within the Hardware Manager.
Note: Either the
“Table” or “Chart” view can be used to look at the window.
Figure 1. Example Read Calibration Margin from Memory IP Debug
GUI
This is a sample of results for the Read Per-Bit Deskew XSDB debug signals:
BRAM_RDDQ_IDELAY_FINAL_BIT00 int true 59
BRAM_RDDQ_IDELAY_FINAL_BIT01 int true 70
BRAM_RDDQ_IDELAY_FINAL_BIT02 int true 58
BRAM_RDDQ_IDELAY_FINAL_BIT03 int true 61
BRAM_RDDQ_IDELAY_FINAL_BIT04 int true 69
BRAM_RDDQ_IDELAY_FINAL_BIT05 int true 78
BRAM_RDDQ_IDELAY_FINAL_BIT06 int true 73
BRAM_RDDQ_IDELAY_FINAL_BIT07 int true 73
BRAM_RDDQ_IDELAY_FINAL_BIT08 int true 63
BRAM_RDDQ_IDELAY_FINAL_BIT09 int true 70
BRAM_RDDQ_IDELAY_FINAL_BIT10 int true 55
BRAM_RDDQ_IDELAY_FINAL_BIT11 int true 63
BRAM_RDDQ_IDELAY_FINAL_BIT12 int true 76
BRAM_RDDQ_IDELAY_FINAL_BIT13 int true 68
BRAM_RDDQ_IDELAY_FINAL_BIT14 int true 68
BRAM_RDDQ_IDELAY_FINAL_BIT15 int true 60
BRAM_RDDQ_IDELAY_FINAL_BIT16 int true 71
BRAM_RDDQ_IDELAY_FINAL_BIT17 int true 70
BRAM_RDDQ_IDELAY_FINAL_BIT18 int true 69
BRAM_RDDQ_IDELAY_FINAL_BIT19 int true 73
BRAM_RDDQ_IDELAY_FINAL_BIT20 int true 61
BRAM_RDDQ_IDELAY_FINAL_BIT21 int true 75
BRAM_RDDQ_IDELAY_FINAL_BIT22 int true 71
BRAM_RDDQ_IDELAY_FINAL_BIT23 int true 77
BRAM_RDDQ_IDELAY_FINAL_BIT24 int true 63
BRAM_RDDQ_IDELAY_FINAL_BIT25 int true 69
BRAM_RDDQ_IDELAY_FINAL_BIT26 int true 60
BRAM_RDDQ_IDELAY_FINAL_BIT27 int true 62
BRAM_RDDQ_IDELAY_FINAL_BIT28 int true 68
BRAM_RDDQ_IDELAY_FINAL_BIT29 int true 70
BRAM_RDDQ_IDELAY_FINAL_BIT30 int true 67
BRAM_RDDQ_IDELAY_FINAL_BIT31 int true 71
BRAM_RDDQ_IDELAY_FINAL_BIT32 int true 64
BRAM_RDDQ_IDELAY_FINAL_BIT33 int true 66
BRAM_RDDQ_IDELAY_FINAL_BIT34 int true 55
BRAM_RDDQ_IDELAY_FINAL_BIT35 int true 61
BRAM_RDDQ_IDELAY_FINAL_BIT36 int true 63
BRAM_RDDQ_IDELAY_FINAL_BIT37 int true 69
BRAM_RDDQ_IDELAY_FINAL_BIT38 int true 69
BRAM_RDDQ_IDELAY_FINAL_BIT39 int true 69
BRAM_RDDQ_IDELAY_FINAL_BIT40 int true 66
BRAM_RDDQ_IDELAY_FINAL_BIT41 int true 63
BRAM_RDDQ_IDELAY_FINAL_BIT42 int true 61
BRAM_RDDQ_IDELAY_FINAL_BIT43 int true 62
BRAM_RDDQ_IDELAY_FINAL_BIT44 int true 67
BRAM_RDDQ_IDELAY_FINAL_BIT45 int true 67
BRAM_RDDQ_IDELAY_FINAL_BIT46 int true 69
BRAM_RDDQ_IDELAY_FINAL_BIT47 int true 69
BRAM_RDDQ_IDELAY_FINAL_BIT48 int true 73
BRAM_RDDQ_IDELAY_FINAL_BIT49 int true 75
BRAM_RDDQ_IDELAY_FINAL_BIT50 int true 68
BRAM_RDDQ_IDELAY_FINAL_BIT51 int true 65
BRAM_RDDQ_IDELAY_FINAL_BIT52 int true 67
BRAM_RDDQ_IDELAY_FINAL_BIT53 int true 77
BRAM_RDDQ_IDELAY_FINAL_BIT54 int true 77
BRAM_RDDQ_IDELAY_FINAL_BIT55 int true 73
BRAM_RDDQ_IDELAY_FINAL_BIT56 int true 61
BRAM_RDDQ_IDELAY_FINAL_BIT57 int true 75
BRAM_RDDQ_IDELAY_FINAL_BIT58 int true 68
BRAM_RDDQ_IDELAY_FINAL_BIT59 int true 67
BRAM_RDDQ_IDELAY_FINAL_BIT60 int true 68
BRAM_RDDQ_IDELAY_FINAL_BIT61 int true 77
BRAM_RDDQ_IDELAY_FINAL_BIT62 int true 73
BRAM_RDDQ_IDELAY_FINAL_BIT63 int true 74
BRAM_RDDQ_PQTR_LEFT_NIBBLE0 int true 22
BRAM_RDDQ_PQTR_LEFT_NIBBLE1 int true 22
BRAM_RDDQ_PQTR_LEFT_NIBBLE2 int true 22
BRAM_RDDQ_PQTR_LEFT_NIBBLE3 int true 22
BRAM_RDDQ_PQTR_LEFT_NIBBLE4 int true 22
BRAM_RDDQ_PQTR_LEFT_NIBBLE5 int true 22
BRAM_RDDQ_PQTR_LEFT_NIBBLE6 int true 22
BRAM_RDDQ_PQTR_LEFT_NIBBLE7 int true 22
BRAM_RDDQ_PQTR_LEFT_NIBBLE8 int true 22
BRAM_RDDQ_PQTR_LEFT_NIBBLE9 int true 22
BRAM_RDDQ_PQTR_LEFT_NIBBLE10 int true 22
BRAM_RDDQ_PQTR_LEFT_NIBBLE11 int true 22
BRAM_RDDQ_PQTR_LEFT_NIBBLE12 int true 22
BRAM_RDDQ_PQTR_LEFT_NIBBLE13 int true 22
BRAM_RDDQ_PQTR_LEFT_NIBBLE14 int true 22
BRAM_RDDQ_PQTR_LEFT_NIBBLE15 int true 22
BRAM_RDDQ_NQTR_LEFT_NIBBLE0 int true 33
BRAM_RDDQ_NQTR_LEFT_NIBBLE1 int true 42
BRAM_RDDQ_NQTR_LEFT_NIBBLE2 int true 37
BRAM_RDDQ_NQTR_LEFT_NIBBLE3 int true 60
BRAM_RDDQ_NQTR_LEFT_NIBBLE4 int true 42
BRAM_RDDQ_NQTR_LEFT_NIBBLE5 int true 39
BRAM_RDDQ_NQTR_LEFT_NIBBLE6 int true 43
BRAM_RDDQ_NQTR_LEFT_NIBBLE7 int true 42
BRAM_RDDQ_NQTR_LEFT_NIBBLE8 int true 37
BRAM_RDDQ_NQTR_LEFT_NIBBLE9 int true 42
BRAM_RDDQ_NQTR_LEFT_NIBBLE10 int true 40
BRAM_RDDQ_NQTR_LEFT_NIBBLE11 int true 43
BRAM_RDDQ_NQTR_LEFT_NIBBLE12 int true 42
BRAM_RDDQ_NQTR_LEFT_NIBBLE13 int true 39
BRAM_RDDQ_NQTR_LEFT_NIBBLE14 int true 36
BRAM_RDDQ_NQTR_LEFT_NIBBLE15 int true 39
BRAM_RDDQ_PQTR_RIGHT_FCRSE_NIBBLE0 int true 192
BRAM_RDDQ_PQTR_RIGHT_FCRSE_NIBBLE1 int true 192
BRAM_RDDQ_PQTR_RIGHT_FCRSE_NIBBLE2 int true 192
BRAM_RDDQ_PQTR_RIGHT_FCRSE_NIBBLE3 int true 192
BRAM_RDDQ_PQTR_RIGHT_FCRSE_NIBBLE4 int true 192
BRAM_RDDQ_PQTR_RIGHT_FCRSE_NIBBLE5 int true 202
BRAM_RDDQ_PQTR_RIGHT_FCRSE_NIBBLE6 int true 192
BRAM_RDDQ_PQTR_RIGHT_FCRSE_NIBBLE7 int true 192
BRAM_RDDQ_PQTR_RIGHT_FCRSE_NIBBLE8 int true 0
BRAM_RDDQ_PQTR_RIGHT_FCRSE_NIBBLE9 int true 0
BRAM_RDDQ_PQTR_RIGHT_FCRSE_NIBBLE10 int true 0
BRAM_RDDQ_PQTR_RIGHT_FCRSE_NIBBLE11 int true 0
BRAM_RDDQ_PQTR_RIGHT_FCRSE_NIBBLE12 int true 0
BRAM_RDDQ_PQTR_RIGHT_FCRSE_NIBBLE13 int true 0
BRAM_RDDQ_PQTR_RIGHT_FCRSE_NIBBLE14 int true 0
BRAM_RDDQ_PQTR_RIGHT_FCRSE_NIBBLE15 int true 0
BRAM_RDDQ_NQTR_RIGHT_FCRSE_NIBBLE0 int true 183
BRAM_RDDQ_NQTR_RIGHT_FCRSE_NIBBLE1 int true 192
BRAM_RDDQ_NQTR_RIGHT_FCRSE_NIBBLE2 int true 187
BRAM_RDDQ_NQTR_RIGHT_FCRSE_NIBBLE3 int true 200
BRAM_RDDQ_NQTR_RIGHT_FCRSE_NIBBLE4 int true 182
BRAM_RDDQ_NQTR_RIGHT_FCRSE_NIBBLE5 int true 189
BRAM_RDDQ_NQTR_RIGHT_FCRSE_NIBBLE6 int true 193
BRAM_RDDQ_NQTR_RIGHT_FCRSE_NIBBLE7 int true 192
BRAM_RDDQ_NQTR_RIGHT_FCRSE_NIBBLE8 int true 0
BRAM_RDDQ_NQTR_RIGHT_FCRSE_NIBBLE9 int true 0
BRAM_RDDQ_NQTR_RIGHT_FCRSE_NIBBLE10 int true 0
BRAM_RDDQ_NQTR_RIGHT_FCRSE_NIBBLE11 int true 0
BRAM_RDDQ_NQTR_RIGHT_FCRSE_NIBBLE12 int true 0
BRAM_RDDQ_NQTR_RIGHT_FCRSE_NIBBLE13 int true 0
BRAM_RDDQ_NQTR_RIGHT_FCRSE_NIBBLE14 int true 0
BRAM_RDDQ_NQTR_RIGHT_FCRSE_NIBBLE15 int true 0
BRAM_RDDQ_PQTR_RIGHT_NIBBLE0 int true 172
BRAM_RDDQ_PQTR_RIGHT_NIBBLE1 int true 175
BRAM_RDDQ_PQTR_RIGHT_NIBBLE2 int true 172
BRAM_RDDQ_PQTR_RIGHT_NIBBLE3 int true 172
BRAM_RDDQ_PQTR_RIGHT_NIBBLE4 int true 174
BRAM_RDDQ_PQTR_RIGHT_NIBBLE5 int true 179
BRAM_RDDQ_PQTR_RIGHT_NIBBLE6 int true 172
BRAM_RDDQ_PQTR_RIGHT_NIBBLE7 int true 175
BRAM_RDDQ_PQTR_RIGHT_NIBBLE8 int true 175
BRAM_RDDQ_PQTR_RIGHT_NIBBLE9 int true 176
BRAM_RDDQ_PQTR_RIGHT_NIBBLE10 int true 175
BRAM_RDDQ_PQTR_RIGHT_NIBBLE11 int true 176
BRAM_RDDQ_PQTR_RIGHT_NIBBLE12 int true 176
BRAM_RDDQ_PQTR_RIGHT_NIBBLE13 int true 173
BRAM_RDDQ_PQTR_RIGHT_NIBBLE14 int true 176
BRAM_RDDQ_PQTR_RIGHT_NIBBLE15 int true 176
BRAM_RDDQ_NQTR_RIGHT_NIBBLE0 int true 167
BRAM_RDDQ_NQTR_RIGHT_NIBBLE1 int true 172
BRAM_RDDQ_NQTR_RIGHT_NIBBLE2 int true 170
BRAM_RDDQ_NQTR_RIGHT_NIBBLE3 int true 175
BRAM_RDDQ_NQTR_RIGHT_NIBBLE4 int true 165
BRAM_RDDQ_NQTR_RIGHT_NIBBLE5 int true 168
BRAM_RDDQ_NQTR_RIGHT_NIBBLE6 int true 172
BRAM_RDDQ_NQTR_RIGHT_NIBBLE7 int true 171
BRAM_RDDQ_NQTR_RIGHT_NIBBLE8 int true 164
BRAM_RDDQ_NQTR_RIGHT_NIBBLE9 int true 166
BRAM_RDDQ_NQTR_RIGHT_NIBBLE10 int true 171
BRAM_RDDQ_NQTR_RIGHT_NIBBLE11 int true 170
BRAM_RDDQ_NQTR_RIGHT_NIBBLE12 int true 166
BRAM_RDDQ_NQTR_RIGHT_NIBBLE13 int true 166
BRAM_RDDQ_NQTR_RIGHT_NIBBLE14 int true 166
BRAM_RDDQ_NQTR_RIGHT_NIBBLE15 int true 168
BRAM_RDDQ_PQTR_FINAL_NIBBLE0 int true 97
BRAM_RDDQ_PQTR_FINAL_NIBBLE1 int true 98
BRAM_RDDQ_PQTR_FINAL_NIBBLE2 int true 97
BRAM_RDDQ_PQTR_FINAL_NIBBLE3 int true 97
BRAM_RDDQ_PQTR_FINAL_NIBBLE4 int true 98
BRAM_RDDQ_PQTR_FINAL_NIBBLE5 int true 100
BRAM_RDDQ_PQTR_FINAL_NIBBLE6 int true 97
BRAM_RDDQ_PQTR_FINAL_NIBBLE7 int true 98
BRAM_RDDQ_PQTR_FINAL_NIBBLE8 int true 98
BRAM_RDDQ_PQTR_FINAL_NIBBLE9 int true 99
BRAM_RDDQ_PQTR_FINAL_NIBBLE10 int true 98
BRAM_RDDQ_PQTR_FINAL_NIBBLE11 int true 99
BRAM_RDDQ_PQTR_FINAL_NIBBLE12 int true 99
BRAM_RDDQ_PQTR_FINAL_NIBBLE13 int true 97
BRAM_RDDQ_PQTR_FINAL_NIBBLE14 int true 99
BRAM_RDDQ_PQTR_FINAL_NIBBLE15 int true 99
BRAM_RDDQ_NQTR_FINAL_NIBBLE0 int true 100
BRAM_RDDQ_NQTR_FINAL_NIBBLE1 int true 107
BRAM_RDDQ_NQTR_FINAL_NIBBLE2 int true 103
BRAM_RDDQ_NQTR_FINAL_NIBBLE3 int true 117
BRAM_RDDQ_NQTR_FINAL_NIBBLE4 int true 103
BRAM_RDDQ_NQTR_FINAL_NIBBLE5 int true 103
BRAM_RDDQ_NQTR_FINAL_NIBBLE6 int true 107
BRAM_RDDQ_NQTR_FINAL_NIBBLE7 int true 106
BRAM_RDDQ_NQTR_FINAL_NIBBLE8 int true 100
BRAM_RDDQ_NQTR_FINAL_NIBBLE9 int true 104
BRAM_RDDQ_NQTR_FINAL_NIBBLE10 int true 105
BRAM_RDDQ_NQTR_FINAL_NIBBLE11 int true 106
BRAM_RDDQ_NQTR_FINAL_NIBBLE12 int true 104
BRAM_RDDQ_NQTR_FINAL_NIBBLE13 int true 102
BRAM_RDDQ_NQTR_FINAL_NIBBLE14 int true 101
BRAM_RDDQ_NQTR_FINAL_NIBBLE15 int true 103
BRAM_BISC_PQTR_ALIGN_NIBBLE0 int true 1
BRAM_BISC_PQTR_ALIGN_NIBBLE1 int true 0
BRAM_BISC_PQTR_ALIGN_NIBBLE2 int true 1
BRAM_BISC_PQTR_ALIGN_NIBBLE3 int true 0
BRAM_BISC_PQTR_ALIGN_NIBBLE4 int true 0
BRAM_BISC_PQTR_ALIGN_NIBBLE5 int true 2
BRAM_BISC_PQTR_ALIGN_NIBBLE6 int true 0
BRAM_BISC_PQTR_ALIGN_NIBBLE7 int true 0
BRAM_BISC_PQTR_ALIGN_NIBBLE8 int true 1
BRAM_BISC_PQTR_ALIGN_NIBBLE9 int true 1
BRAM_BISC_PQTR_ALIGN_NIBBLE10 int true 0
BRAM_BISC_PQTR_ALIGN_NIBBLE11 int true 33
BRAM_BISC_PQTR_ALIGN_NIBBLE12 int true 0
BRAM_BISC_PQTR_ALIGN_NIBBLE13 int true 1
BRAM_BISC_PQTR_ALIGN_NIBBLE14 int true 1
BRAM_BISC_PQTR_ALIGN_NIBBLE15 int true 2
BRAM_BISC_NQTR_ALIGN_NIBBLE0 int true 0
BRAM_BISC_NQTR_ALIGN_NIBBLE1 int true 1
BRAM_BISC_NQTR_ALIGN_NIBBLE2 int true 0
BRAM_BISC_NQTR_ALIGN_NIBBLE3 int true 1
BRAM_BISC_NQTR_ALIGN_NIBBLE4 int true 0
BRAM_BISC_NQTR_ALIGN_NIBBLE5 int true 0
BRAM_BISC_NQTR_ALIGN_NIBBLE6 int true 2
BRAM_BISC_NQTR_ALIGN_NIBBLE7 int true 0
BRAM_BISC_NQTR_ALIGN_NIBBLE8 int true 0
BRAM_BISC_NQTR_ALIGN_NIBBLE9 int true 0
BRAM_BISC_NQTR_ALIGN_NIBBLE10 int true 1
BRAM_BISC_NQTR_ALIGN_NIBBLE11 int true 0
BRAM_BISC_NQTR_ALIGN_NIBBLE12 int true 1
BRAM_BISC_NQTR_ALIGN_NIBBLE13 int true 0
BRAM_BISC_NQTR_ALIGN_NIBBLE14 int true 0
BRAM_BISC_NQTR_ALIGN_NIBBLE15 int true 0
BRAM_BISC_PQTR_NIBBLE0 int true 89
BRAM_BISC_PQTR_NIBBLE1 int true 88
BRAM_BISC_PQTR_NIBBLE2 int true 89
BRAM_BISC_PQTR_NIBBLE3 int true 87
BRAM_BISC_PQTR_NIBBLE4 int true 88
BRAM_BISC_PQTR_NIBBLE5 int true 88
BRAM_BISC_PQTR_NIBBLE6 int true 89
BRAM_BISC_PQTR_NIBBLE7 int true 88
BRAM_BISC_PQTR_NIBBLE8 int true 88
BRAM_BISC_PQTR_NIBBLE9 int true 91
BRAM_BISC_PQTR_NIBBLE10 int true 90
BRAM_BISC_PQTR_NIBBLE11 int true 92
BRAM_BISC_PQTR_NIBBLE12 int true 89
BRAM_BISC_PQTR_NIBBLE13 int true 90
BRAM_BISC_PQTR_NIBBLE14 int true 90
BRAM_BISC_PQTR_NIBBLE15 int true 90
BRAM_BISC_NQTR_NIBBLE0 int true 87
BRAM_BISC_NQTR_NIBBLE1 int true 90
BRAM_BISC_NQTR_NIBBLE2 int true 90
BRAM_BISC_NQTR_NIBBLE3 int true 89
BRAM_BISC_NQTR_NIBBLE4 int true 87
BRAM_BISC_NQTR_NIBBLE5 int true 89
BRAM_BISC_NQTR_NIBBLE6 int true 91
BRAM_BISC_NQTR_NIBBLE7 int true 91
BRAM_BISC_NQTR_NIBBLE8 int true 87
BRAM_BISC_NQTR_NIBBLE9 int true 91
BRAM_BISC_NQTR_NIBBLE10 int true 90
BRAM_BISC_NQTR_NIBBLE11 int true 91
BRAM_BISC_NQTR_NIBBLE12 int true 90
BRAM_BISC_NQTR_NIBBLE13 int true 90
BRAM_BISC_NQTR_NIBBLE14 int true 88
BRAM_BISC_NQTR_NIBBLE15 int true 89