The following table shows the XSDB registers and values adjusted or used during the Read Per-Bit DQ Deskew stage of calibration. The values can be analyzed in both successful and failing calibrations to determine the resultant values and the consistency in results across resets. These values can be found within the Memory IP core properties in the Hardware Manager or by executing the Tcl commands noted in the Manually Analyzing the XSDB Output section.
| XSDB Reg | Usage | Signal Description |
|---|---|---|
| BRAM_RDDQ_QTR_DESKEW_NIBBLE* | One per nibble | Read leveling QTR IDELAY (PDQS and NDQS delayed together) delay value when valid stable region is detected for all DQ bits in a nibble during per bit read DQ deskew. |
| BRAM_RDDQ_IDELAY_FINAL_BIT* | One per bit | Read leveling IDELAY delay value found during per bit read DQ deskew. |
This is a sample of the results for the Read Per-Bit DQ Deskew XSDB debug signals:
BRAM_RDDQ_QTR_DESKEW_NIBBLE0 int true 16
BRAM_RDDQ_QTR_DESKEW_NIBBLE1 int true 16
BRAM_RDDQ_QTR_DESKEW_NIBBLE2 int true 16
BRAM_RDDQ_QTR_DESKEW_NIBBLE3 int true 16
BRAM_RDDQ_QTR_DESKEW_NIBBLE4 int true 16
BRAM_RDDQ_QTR_DESKEW_NIBBLE5 int true 16
BRAM_RDDQ_QTR_DESKEW_NIBBLE6 int true 16
BRAM_RDDQ_QTR_DESKEW_NIBBLE7 int true 16
BRAM_RDDQ_QTR_DESKEW_NIBBLE8 int true 0
BRAM_RDDQ_QTR_DESKEW_NIBBLE9 int true 0
BRAM_RDDQ_QTR_DESKEW_NIBBLE10 int true 0
BRAM_RDDQ_QTR_DESKEW_NIBBLE11 int true 0
BRAM_RDDQ_QTR_DESKEW_NIBBLE12 int true 0
BRAM_RDDQ_QTR_DESKEW_NIBBLE13 int true 0
BRAM_RDDQ_QTR_DESKEW_NIBBLE14 int true 0
BRAM_RDDQ_QTR_DESKEW_NIBBLE15 int true 0
BRAM_RDDQ_IDELAY_FINAL_BIT00 int true 59
BRAM_RDDQ_IDELAY_FINAL_BIT01 int true 70
BRAM_RDDQ_IDELAY_FINAL_BIT02 int true 58
BRAM_RDDQ_IDELAY_FINAL_BIT03 int true 61
BRAM_RDDQ_IDELAY_FINAL_BIT04 int true 69
BRAM_RDDQ_IDELAY_FINAL_BIT05 int true 78
BRAM_RDDQ_IDELAY_FINAL_BIT06 int true 73
BRAM_RDDQ_IDELAY_FINAL_BIT07 int true 73
BRAM_RDDQ_IDELAY_FINAL_BIT08 int true 63
BRAM_RDDQ_IDELAY_FINAL_BIT09 int true 70
BRAM_RDDQ_IDELAY_FINAL_BIT10 int true 55
BRAM_RDDQ_IDELAY_FINAL_BIT11 int true 63
BRAM_RDDQ_IDELAY_FINAL_BIT12 int true 76
BRAM_RDDQ_IDELAY_FINAL_BIT13 int true 68
BRAM_RDDQ_IDELAY_FINAL_BIT14 int true 68
BRAM_RDDQ_IDELAY_FINAL_BIT15 int true 60
BRAM_RDDQ_IDELAY_FINAL_BIT16 int true 71
BRAM_RDDQ_IDELAY_FINAL_BIT17 int true 70
BRAM_RDDQ_IDELAY_FINAL_BIT18 int true 69
BRAM_RDDQ_IDELAY_FINAL_BIT19 int true 73
BRAM_RDDQ_IDELAY_FINAL_BIT20 int true 61
BRAM_RDDQ_IDELAY_FINAL_BIT21 int true 75
BRAM_RDDQ_IDELAY_FINAL_BIT22 int true 71
BRAM_RDDQ_IDELAY_FINAL_BIT23 int true 77
BRAM_RDDQ_IDELAY_FINAL_BIT24 int true 63
BRAM_RDDQ_IDELAY_FINAL_BIT25 int true 69
BRAM_RDDQ_IDELAY_FINAL_BIT26 int true 60
BRAM_RDDQ_IDELAY_FINAL_BIT27 int true 62
BRAM_RDDQ_IDELAY_FINAL_BIT28 int true 68
BRAM_RDDQ_IDELAY_FINAL_BIT29 int true 70
BRAM_RDDQ_IDELAY_FINAL_BIT30 int true 67
BRAM_RDDQ_IDELAY_FINAL_BIT31 int true 71
BRAM_RDDQ_IDELAY_FINAL_BIT32 int true 64
BRAM_RDDQ_IDELAY_FINAL_BIT33 int true 66
BRAM_RDDQ_IDELAY_FINAL_BIT34 int true 55
BRAM_RDDQ_IDELAY_FINAL_BIT35 int true 61
BRAM_RDDQ_IDELAY_FINAL_BIT36 int true 63
BRAM_RDDQ_IDELAY_FINAL_BIT37 int true 69
BRAM_RDDQ_IDELAY_FINAL_BIT38 int true 69
BRAM_RDDQ_IDELAY_FINAL_BIT39 int true 69
BRAM_RDDQ_IDELAY_FINAL_BIT40 int true 66
BRAM_RDDQ_IDELAY_FINAL_BIT41 int true 63
BRAM_RDDQ_IDELAY_FINAL_BIT42 int true 61
BRAM_RDDQ_IDELAY_FINAL_BIT43 int true 62
BRAM_RDDQ_IDELAY_FINAL_BIT44 int true 67
BRAM_RDDQ_IDELAY_FINAL_BIT45 int true 67
BRAM_RDDQ_IDELAY_FINAL_BIT46 int true 69
BRAM_RDDQ_IDELAY_FINAL_BIT47 int true 69
BRAM_RDDQ_IDELAY_FINAL_BIT48 int true 73
BRAM_RDDQ_IDELAY_FINAL_BIT49 int true 75
BRAM_RDDQ_IDELAY_FINAL_BIT50 int true 68
BRAM_RDDQ_IDELAY_FINAL_BIT51 int true 65
BRAM_RDDQ_IDELAY_FINAL_BIT52 int true 67
BRAM_RDDQ_IDELAY_FINAL_BIT53 int true 77
BRAM_RDDQ_IDELAY_FINAL_BIT54 int true 77
BRAM_RDDQ_IDELAY_FINAL_BIT55 int true 73
BRAM_RDDQ_IDELAY_FINAL_BIT56 int true 61
BRAM_RDDQ_IDELAY_FINAL_BIT57 int true 75
BRAM_RDDQ_IDELAY_FINAL_BIT58 int true 68
BRAM_RDDQ_IDELAY_FINAL_BIT59 int true 67
BRAM_RDDQ_IDELAY_FINAL_BIT60 int true 68
BRAM_RDDQ_IDELAY_FINAL_BIT61 int true 77
BRAM_RDDQ_IDELAY_FINAL_BIT62 int true 73
BRAM_RDDQ_IDELAY_FINAL_BIT63 int true 74