The following table shows the XSDB registers and values adjusted or used during the Write DQS to DQ/DBI Centering stage of calibration. The values can be analyzed in both successful and failing calibrations to determine the resultant values and the consistency in results across resets. These values can be found within the Memory IP core properties in the Hardware Manager or by executing the Tcl commands noted in the Manually Analyzing the XSDB Output section.
| XSDB Reg | Usage | Signal Description |
|---|---|---|
| BRAM_WRDQDBI_LEFT_MARGIN_BYTE* | One per byte | Write data left margin. |
| BRAM_WRDQDBI_LEFT_EDGE_DQ_BIT* | One per byte | DQ ODELAY value at the left edge of write data window. |
| BRAM_WRDQDBI_LEFT_EDGE_DBI_BYTE* | One per byte | DBI ODELAY value at the left edge of write data window. |
| BRAM_WRDQDBI_RIGHT_MARGIN_FCRSE_BYTE* | One per byte | DQS ODELAY value when right edge of write data valid window is detected by incrementing DQS ODELAY using step size of 10 taps (Simple). |
| BRAM_WRDQDBI_RIGHT_MARGIN_BYTE* | One per byte | DQS ODELAY value when right edge of write data valid window is detected by incrementing DQS ODELAY using step size of 1 tap (Simple). |
| BRAM_WRDQDBI_RIGHT_EDGE_DQS_BYTE* | One per byte | |
| BRAM_WRDQDBI_ODLY_DQS_FINAL_BYTE* | One per byte | Final DQS ODELAY value after Write DQS-to-DQ/DBI Centering (Simple). |
| BRAM_WRDQDBI_ODLY_DQ_FINAL_BIT* | One per byte | Final DQ ODELAY value after Write DQS-to-DQ/DBI Centering (Simple). |
| BRAM_WRDQDBI_ODLY_DBI_FINAL_BYTE* | One per byte | Final DBI ODELAY value after Write DQS-to-DQ/DBI Centering (Simple). |
This is a sample of the results for the Write DQ Per-Bit Deskew XSDB debug signals:
BRAM_WRDQDBI_LEFT_MARGIN_BYTE0 int true 66
BRAM_WRDQDBI_LEFT_MARGIN_BYTE1 int true 61
BRAM_WRDQDBI_LEFT_MARGIN_BYTE2 int true 66
BRAM_WRDQDBI_LEFT_MARGIN_BYTE3 int true 73
BRAM_WRDQDBI_LEFT_MARGIN_BYTE4 int true 70
BRAM_WRDQDBI_LEFT_MARGIN_BYTE5 int true 63
BRAM_WRDQDBI_LEFT_MARGIN_BYTE6 int true 75
BRAM_WRDQDBI_LEFT_MARGIN_BYTE7 int true 64
BRAM_WRDQDBI_LEFT_EDGE_DQ_BIT00 int true 31
BRAM_WRDQDBI_LEFT_EDGE_DQ_BIT01 int true 39
BRAM_WRDQDBI_LEFT_EDGE_DQ_BIT02 int true 33
BRAM_WRDQDBI_LEFT_EDGE_DQ_BIT03 int true 43
BRAM_WRDQDBI_LEFT_EDGE_DQ_BIT04 int true 42
BRAM_WRDQDBI_LEFT_EDGE_DQ_BIT05 int true 48
BRAM_WRDQDBI_LEFT_EDGE_DQ_BIT06 int true 42
BRAM_WRDQDBI_LEFT_EDGE_DQ_BIT07 int true 42
BRAM_WRDQDBI_LEFT_EDGE_DQ_BIT08 int true 69
BRAM_WRDQDBI_LEFT_EDGE_DQ_BIT09 int true 69
BRAM_WRDQDBI_LEFT_EDGE_DQ_BIT10 int true 70
BRAM_WRDQDBI_LEFT_EDGE_DQ_BIT11 int true 75
BRAM_WRDQDBI_LEFT_EDGE_DQ_BIT12 int true 70
BRAM_WRDQDBI_LEFT_EDGE_DQ_BIT13 int true 78
BRAM_WRDQDBI_LEFT_EDGE_DQ_BIT14 int true 70
BRAM_WRDQDBI_LEFT_EDGE_DQ_BIT15 int true 63
BRAM_WRDQDBI_LEFT_EDGE_DQ_BIT16 int true 113
BRAM_WRDQDBI_LEFT_EDGE_DQ_BIT17 int true 114
BRAM_WRDQDBI_LEFT_EDGE_DQ_BIT18 int true 113
BRAM_WRDQDBI_LEFT_EDGE_DQ_BIT19 int true 123
BRAM_WRDQDBI_LEFT_EDGE_DQ_BIT20 int true 105
BRAM_WRDQDBI_LEFT_EDGE_DQ_BIT21 int true 118
BRAM_WRDQDBI_LEFT_EDGE_DQ_BIT22 int true 116
BRAM_WRDQDBI_LEFT_EDGE_DQ_BIT23 int true 121
BRAM_WRDQDBI_LEFT_EDGE_DQ_BIT24 int true 97
BRAM_WRDQDBI_LEFT_EDGE_DQ_BIT25 int true 98
BRAM_WRDQDBI_LEFT_EDGE_DQ_BIT26 int true 93
BRAM_WRDQDBI_LEFT_EDGE_DQ_BIT27 int true 103
BRAM_WRDQDBI_LEFT_EDGE_DQ_BIT28 int true 97
BRAM_WRDQDBI_LEFT_EDGE_DQ_BIT29 int true 96
BRAM_WRDQDBI_LEFT_EDGE_DQ_BIT30 int true 101
BRAM_WRDQDBI_LEFT_EDGE_DQ_BIT31 int true 103
BRAM_WRDQDBI_LEFT_EDGE_DQ_BIT32 int true 62
BRAM_WRDQDBI_LEFT_EDGE_DQ_BIT33 int true 61
BRAM_WRDQDBI_LEFT_EDGE_DQ_BIT34 int true 59
BRAM_WRDQDBI_LEFT_EDGE_DQ_BIT35 int true 63
BRAM_WRDQDBI_LEFT_EDGE_DQ_BIT36 int true 59
BRAM_WRDQDBI_LEFT_EDGE_DQ_BIT37 int true 75
BRAM_WRDQDBI_LEFT_EDGE_DQ_BIT38 int true 68
BRAM_WRDQDBI_LEFT_EDGE_DQ_BIT39 int true 68
BRAM_WRDQDBI_LEFT_EDGE_DQ_BIT40 int true 31
BRAM_WRDQDBI_LEFT_EDGE_DQ_BIT41 int true 30
BRAM_WRDQDBI_LEFT_EDGE_DQ_BIT42 int true 30
BRAM_WRDQDBI_LEFT_EDGE_DQ_BIT43 int true 41
BRAM_WRDQDBI_LEFT_EDGE_DQ_BIT44 int true 28
BRAM_WRDQDBI_LEFT_EDGE_DQ_BIT45 int true 39
BRAM_WRDQDBI_LEFT_EDGE_DQ_BIT46 int true 35
BRAM_WRDQDBI_LEFT_EDGE_DQ_BIT47 int true 38
BRAM_WRDQDBI_LEFT_EDGE_DQ_BIT48 int true 61
BRAM_WRDQDBI_LEFT_EDGE_DQ_BIT49 int true 59
BRAM_WRDQDBI_LEFT_EDGE_DQ_BIT50 int true 55
BRAM_WRDQDBI_LEFT_EDGE_DQ_BIT51 int true 59
BRAM_WRDQDBI_LEFT_EDGE_DQ_BIT52 int true 57
BRAM_WRDQDBI_LEFT_EDGE_DQ_BIT53 int true 63
BRAM_WRDQDBI_LEFT_EDGE_DQ_BIT54 int true 63
BRAM_WRDQDBI_LEFT_EDGE_DQ_BIT55 int true 66
BRAM_WRDQDBI_LEFT_EDGE_DQ_BIT56 int true 99
BRAM_WRDQDBI_LEFT_EDGE_DQ_BIT57 int true 114
BRAM_WRDQDBI_LEFT_EDGE_DQ_BIT58 int true 114
BRAM_WRDQDBI_LEFT_EDGE_DQ_BIT59 int true 117
BRAM_WRDQDBI_LEFT_EDGE_DQ_BIT60 int true 113
BRAM_WRDQDBI_LEFT_EDGE_DQ_BIT61 int true 118
BRAM_WRDQDBI_LEFT_EDGE_DQ_BIT62 int true 114
BRAM_WRDQDBI_LEFT_EDGE_DQ_BIT63 int true 118
BRAM_WRDQDBI_LEFT_EDGE_DBI_BYTE0 int true 39
BRAM_WRDQDBI_LEFT_EDGE_DBI_BYTE1 int true 76
BRAM_WRDQDBI_LEFT_EDGE_DBI_BYTE2 int true 119
BRAM_WRDQDBI_LEFT_EDGE_DBI_BYTE3 int true 102
BRAM_WRDQDBI_LEFT_EDGE_DBI_BYTE4 int true 67
BRAM_WRDQDBI_LEFT_EDGE_DBI_BYTE5 int true 38
BRAM_WRDQDBI_LEFT_EDGE_DBI_BYTE6 int true 66
BRAM_WRDQDBI_LEFT_EDGE_DBI_BYTE7 int true 107
BRAM_WRDQDBI_RIGHT_EDGE_DQS_BYTE0 int true 0
BRAM_WRDQDBI_RIGHT_EDGE_DQS_BYTE1 int true 0
BRAM_WRDQDBI_RIGHT_EDGE_DQS_BYTE2 int true 0
BRAM_WRDQDBI_RIGHT_EDGE_DQS_BYTE3 int true 0
BRAM_WRDQDBI_RIGHT_EDGE_DQS_BYTE4 int true 0
BRAM_WRDQDBI_RIGHT_EDGE_DQS_BYTE5 int true 0
BRAM_WRDQDBI_RIGHT_EDGE_DQS_BYTE6 int true 0
BRAM_WRDQDBI_RIGHT_EDGE_DQS_BYTE7 int true 0
BRAM_WRDQDBI_RIGHT_MARGIN_FCRSE_BYTE0 int true 100
BRAM_WRDQDBI_RIGHT_MARGIN_FCRSE_BYTE1 int true 100
BRAM_WRDQDBI_RIGHT_MARGIN_FCRSE_BYTE2 int true 100
BRAM_WRDQDBI_RIGHT_MARGIN_FCRSE_BYTE3 int true 90
BRAM_WRDQDBI_RIGHT_MARGIN_FCRSE_BYTE4 int true 100
BRAM_WRDQDBI_RIGHT_MARGIN_FCRSE_BYTE5 int true 90
BRAM_WRDQDBI_RIGHT_MARGIN_FCRSE_BYTE6 int true 90
BRAM_WRDQDBI_RIGHT_MARGIN_FCRSE_BYTE7 int true 90
BRAM_WRDQDBI_RIGHT_MARGIN_BYTE0 int true 99
BRAM_WRDQDBI_RIGHT_MARGIN_BYTE1 int true 106
BRAM_WRDQDBI_RIGHT_MARGIN_BYTE2 int true 103
BRAM_WRDQDBI_RIGHT_MARGIN_BYTE3 int true 91
BRAM_WRDQDBI_RIGHT_MARGIN_BYTE4 int true 103
BRAM_WRDQDBI_RIGHT_MARGIN_BYTE7 int true 97
BRAM_WRDQDBI_RIGHT_MARGIN_BYTE5 int true 97
BRAM_WRDQDBI_RIGHT_MARGIN_BYTE6 int true 90
BRAM_WRDQDBI_ODLY_DQS_FINAL_BYTE0 int true 48
BRAM_WRDQDBI_ODLY_DQS_FINAL_BYTE1 int true 86
BRAM_WRDQDBI_ODLY_DQS_FINAL_BYTE2 int true 124
BRAM_WRDQDBI_ODLY_DQS_FINAL_BYTE3 int true 102
BRAM_WRDQDBI_ODLY_DQS_FINAL_BYTE4 int true 76
BRAM_WRDQDBI_ODLY_DQS_FINAL_BYTE5 int true 45
BRAM_WRDQDBI_ODLY_DQS_FINAL_BYTE6 int true 63
BRAM_WRDQDBI_ODLY_DQS_FINAL_BYTE7 int true 116
BRAM_WRDQDBI_ODLY_DQ_FINAL_BIT00 int true 31
BRAM_WRDQDBI_ODLY_DQ_FINAL_BIT01 int true 39
BRAM_WRDQDBI_ODLY_DQ_FINAL_BIT02 int true 33
BRAM_WRDQDBI_ODLY_DQ_FINAL_BIT03 int true 43
BRAM_WRDQDBI_ODLY_DQ_FINAL_BIT04 int true 42
BRAM_WRDQDBI_ODLY_DQ_FINAL_BIT05 int true 48
BRAM_WRDQDBI_ODLY_DQ_FINAL_BIT06 int true 42
BRAM_WRDQDBI_ODLY_DQ_FINAL_BIT07 int true 42
BRAM_WRDQDBI_ODLY_DQ_FINAL_BIT08 int true 69
BRAM_WRDQDBI_ODLY_DQ_FINAL_BIT09 int true 69
BRAM_WRDQDBI_ODLY_DQ_FINAL_BIT10 int true 70
BRAM_WRDQDBI_ODLY_DQ_FINAL_BIT11 int true 75
BRAM_WRDQDBI_ODLY_DQ_FINAL_BIT12 int true 70
BRAM_WRDQDBI_ODLY_DQ_FINAL_BIT13 int true 78
BRAM_WRDQDBI_ODLY_DQ_FINAL_BIT14 int true 70
BRAM_WRDQDBI_ODLY_DQ_FINAL_BIT15 int true 63
BRAM_WRDQDBI_ODLY_DQ_FINAL_BIT16 int true 113
BRAM_WRDQDBI_ODLY_DQ_FINAL_BIT17 int true 114
BRAM_WRDQDBI_ODLY_DQ_FINAL_BIT18 int true 113
BRAM_WRDQDBI_ODLY_DQ_FINAL_BIT19 int true 123
BRAM_WRDQDBI_ODLY_DQ_FINAL_BIT20 int true 105
BRAM_WRDQDBI_ODLY_DQ_FINAL_BIT21 int true 118
BRAM_WRDQDBI_ODLY_DQ_FINAL_BIT22 int true 116
BRAM_WRDQDBI_ODLY_DQ_FINAL_BIT23 int true 121
BRAM_WRDQDBI_ODLY_DQ_FINAL_BIT24 int true 97
BRAM_WRDQDBI_ODLY_DQ_FINAL_BIT25 int true 98
BRAM_WRDQDBI_ODLY_DQ_FINAL_BIT26 int true 93
BRAM_WRDQDBI_ODLY_DQ_FINAL_BIT27 int true 103
BRAM_WRDQDBI_ODLY_DQ_FINAL_BIT28 int true 97
BRAM_WRDQDBI_ODLY_DQ_FINAL_BIT29 int true 96
BRAM_WRDQDBI_ODLY_DQ_FINAL_BIT30 int true 101
BRAM_WRDQDBI_ODLY_DQ_FINAL_BIT31 int true 103
BRAM_WRDQDBI_ODLY_DQ_FINAL_BIT32 int true 62
BRAM_WRDQDBI_ODLY_DQ_FINAL_BIT33 int true 61
BRAM_WRDQDBI_ODLY_DQ_FINAL_BIT34 int true 59
BRAM_WRDQDBI_ODLY_DQ_FINAL_BIT35 int true 63
BRAM_WRDQDBI_ODLY_DQ_FINAL_BIT36 int true 59
BRAM_WRDQDBI_ODLY_DQ_FINAL_BIT37 int true 75
BRAM_WRDQDBI_ODLY_DQ_FINAL_BIT38 int true 68
BRAM_WRDQDBI_ODLY_DQ_FINAL_BIT39 int true 68
BRAM_WRDQDBI_ODLY_DQ_FINAL_BIT40 int true 31
BRAM_WRDQDBI_ODLY_DQ_FINAL_BIT41 int true 30
BRAM_WRDQDBI_ODLY_DQ_FINAL_BIT42 int true 30
BRAM_WRDQDBI_ODLY_DQ_FINAL_BIT43 int true 41
BRAM_WRDQDBI_ODLY_DQ_FINAL_BIT44 int true 28
BRAM_WRDQDBI_ODLY_DQ_FINAL_BIT45 int true 39
BRAM_WRDQDBI_ODLY_DQ_FINAL_BIT46 int true 35
BRAM_WRDQDBI_ODLY_DQ_FINAL_BIT47 int true 38
BRAM_WRDQDBI_ODLY_DQ_FINAL_BIT48 int true 61
BRAM_WRDQDBI_ODLY_DQ_FINAL_BIT49 int true 59
BRAM_WRDQDBI_ODLY_DQ_FINAL_BIT50 int true 55
BRAM_WRDQDBI_ODLY_DQ_FINAL_BIT51 int true 59
BRAM_WRDQDBI_ODLY_DQ_FINAL_BIT52 int true 57
BRAM_WRDQDBI_ODLY_DQ_FINAL_BIT53 int true 63
BRAM_WRDQDBI_ODLY_DQ_FINAL_BIT54 int true 63
BRAM_WRDQDBI_ODLY_DQ_FINAL_BIT55 int true 66
BRAM_WRDQDBI_ODLY_DQ_FINAL_BIT56 int true 99
BRAM_WRDQDBI_ODLY_DQ_FINAL_BIT57 int true 114
BRAM_WRDQDBI_ODLY_DQ_FINAL_BIT58 int true 114
BRAM_WRDQDBI_ODLY_DQ_FINAL_BIT59 int true 117
BRAM_WRDQDBI_ODLY_DQ_FINAL_BIT60 int true 113
BRAM_WRDQDBI_ODLY_DQ_FINAL_BIT61 int true 118
BRAM_WRDQDBI_ODLY_DQ_FINAL_BIT62 int true 114
BRAM_WRDQDBI_ODLY_DQ_FINAL_BIT63 int true 118
BRAM_WRDQDBI_ODLY_DBI_FINAL_BYTE0 int true 39
BRAM_WRDQDBI_ODLY_DBI_FINAL_BYTE1 int true 76
BRAM_WRDQDBI_ODLY_DBI_FINAL_BYTE2 int true 119
BRAM_WRDQDBI_ODLY_DBI_FINAL_BYTE3 int true 102
BRAM_WRDQDBI_ODLY_DBI_FINAL_BYTE4 int true 67
BRAM_WRDQDBI_ODLY_DBI_FINAL_BYTE5 int true 38
BRAM_WRDQDBI_ODLY_DBI_FINAL_BYTE6 int true 66
BRAM_WRDQDBI_ODLY_DBI_FINAL_BYTE7 int true 107