XSDB Registers of Interest during Write DQS to DQ/DBI Centering Complex Calibration - 1.0 English

Versal Adaptive SoC Soft DDR4 SDRAM Memory Controller LogiCORE IP Product Guide (PG353)
Document ID
PG353
Release Date
2023-10-18
Version
1.0 English

The following table shows the XSDB registers and values adjusted or used during the Write Leveling Complex stage of calibration. The values can be analyzed in both successful and failing calibrations to determine the resultant values and the consistency in results across resets. These values can be found within the Memory IP core properties in the Hardware Manager or by executing the Tcl commands noted in the Manually Analyzing the XSDB Output section.

Table 1. XSDB Registers of Interest during Write DQS to DQ/DBI Centering Complex Calibration
XSDB Reg Usage Signal Description
BRAM_WRCMPLX_LEFT_MARGIN_FCRSE_BYTE* One per byte Left edge of write data valid window detected by incrementing DQ/DBI ODELAY using step size of 10 taps (Complex).
BRAM_WRCMPLX_LEFT_MARGIN_BYTE* One per byte Left edge of write data valid window detected by incrementing DQ/DBI ODELAY using step size of 1 tap (Complex).
BRAM_WRCMPLX_RIGHT_MARGIN_FCRSE_BYTE* One per byte Right edge of write data valid window detected by incrementing DQS ODELAY using step size of 10 taps (Complex).
BRAM_WRCMPLX_RIGHT_MARGIN_BYTE* One per byte Right edge of write data valid window detected by incrementing DQS ODELAY using step size of 1 tap (Complex).
BRAM_WRCMPLX_ODLY_DQS_FINAL_BYTE* One per byte Final DQS ODELAY value after Write DQS to DQ/DBI Centering (Complex).
BRAM_WRCMPLX_ODLY_DQ_FINAL_BIT* One per bit Final DQ ODELAY value after Write DQS to DQ/DBI Centering (Complex).
BRAM_WRCMPLX_ODLY_DBI_FINAL_BYTE* One per byte Final DBI ODELAY value after Write DQS to DQ/DBI Centering (Complex).

This is a sample of results for Write DQS to DQ/DBI Centering Complex using the Memory IP Debug GUI within the Hardware Manager.

Note: Either the “Table” or “Chart” view can be used to look at the window.
Figure 1. Example of Complex Write Calibration Margin

This is a sample of the results for the Write DQS to DQ/DBI Centering Complex XSDB debug signals:

BRAM_WRCMPLX_LEFT_MARGIN_FCRSE_BYTE0              int     true       60
BRAM_WRCMPLX_LEFT_MARGIN_FCRSE_BYTE1              int     true       50
BRAM_WRCMPLX_LEFT_MARGIN_FCRSE_BYTE2              int     true       60
BRAM_WRCMPLX_LEFT_MARGIN_FCRSE_BYTE3              int     true       60
BRAM_WRCMPLX_LEFT_MARGIN_FCRSE_BYTE4              int     true       50
BRAM_WRCMPLX_LEFT_MARGIN_FCRSE_BYTE5              int     true       50
BRAM_WRCMPLX_LEFT_MARGIN_FCRSE_BYTE6              int     true       60
BRAM_WRCMPLX_LEFT_MARGIN_FCRSE_BYTE7              int     true       60
BRAM_WRCMPLX_LEFT_MARGIN_BYTE0                    int     true       64
BRAM_WRCMPLX_LEFT_MARGIN_BYTE1                    int     true       58
BRAM_WRCMPLX_LEFT_MARGIN_BYTE2                    int     true       60
BRAM_WRCMPLX_LEFT_MARGIN_BYTE3                    int     true       62
BRAM_WRCMPLX_LEFT_MARGIN_BYTE4                    int     true       59
BRAM_WRCMPLX_LEFT_MARGIN_BYTE5                    int     true       58
BRAM_WRCMPLX_LEFT_MARGIN_BYTE6                    int     true       62
BRAM_WRCMPLX_LEFT_MARGIN_BYTE7                    int     true       65
BRAM_WRCMPLX_RIGHT_MARGIN_FCRSE_BYTE0             int     true       50
BRAM_WRCMPLX_RIGHT_MARGIN_FCRSE_BYTE1             int     true       70
BRAM_WRCMPLX_RIGHT_MARGIN_FCRSE_BYTE2             int     true       70
BRAM_WRCMPLX_RIGHT_MARGIN_FCRSE_BYTE3             int     true       70
BRAM_WRCMPLX_RIGHT_MARGIN_FCRSE_BYTE4             int     true       70
BRAM_WRCMPLX_RIGHT_MARGIN_FCRSE_BYTE5             int     true       60
BRAM_WRCMPLX_RIGHT_MARGIN_FCRSE_BYTE6             int     true       70
BRAM_WRCMPLX_RIGHT_MARGIN_FCRSE_BYTE7             int     true       70
BRAM_WRCMPLX_RIGHT_MARGIN_BYTE0                   int     true       59
BRAM_WRCMPLX_RIGHT_MARGIN_BYTE1                   int     true       72
BRAM_WRCMPLX_RIGHT_MARGIN_BYTE2                   int     true       74
BRAM_WRCMPLX_RIGHT_MARGIN_BYTE3                   int     true       71
BRAM_WRCMPLX_RIGHT_MARGIN_BYTE4                   int     true       74
BRAM_WRCMPLX_RIGHT_MARGIN_BYTE5                   int     true       69
BRAM_WRCMPLX_RIGHT_MARGIN_BYTE6                   int     true       74
BRAM_WRCMPLX_RIGHT_MARGIN_BYTE7                   int     true       76
BRAM_WRCMPLX_ODLY_DQS_FINAL_BYTE0                 int     true       57
BRAM_WRCMPLX_ODLY_DQS_FINAL_BYTE1                 int     true       111
BRAM_WRCMPLX_ODLY_DQS_FINAL_BYTE2                 int     true       87
BRAM_WRCMPLX_ODLY_DQS_FINAL_BYTE3                 int     true       54
BRAM_WRCMPLX_ODLY_DQS_FINAL_BYTE4                 int     true       96
BRAM_WRCMPLX_ODLY_DQS_FINAL_BYTE5                 int     true       89
BRAM_WRCMPLX_ODLY_DQS_FINAL_BYTE6                 int     true       103
BRAM_WRCMPLX_ODLY_DQS_FINAL_BYTE7                 int     true       84
BRAM_WRCMPLX_ODLY_DQ_FINAL_BIT00                  int     true       43
BRAM_WRCMPLX_ODLY_DQ_FINAL_BIT01                  int     true       49
BRAM_WRCMPLX_ODLY_DQ_FINAL_BIT02                  int     true       51
BRAM_WRCMPLX_ODLY_DQ_FINAL_BIT03                  int     true       58
BRAM_WRCMPLX_ODLY_DQ_FINAL_BIT04                  int     true       56
BRAM_WRCMPLX_ODLY_DQ_FINAL_BIT05                  int     true       62
BRAM_WRCMPLX_ODLY_DQ_FINAL_BIT06                  int     true       58
BRAM_WRCMPLX_ODLY_DQ_FINAL_BIT07                  int     true       59
BRAM_WRCMPLX_ODLY_DQ_FINAL_BIT08                  int     true       93
BRAM_WRCMPLX_ODLY_DQ_FINAL_BIT09                  int     true       102
BRAM_WRCMPLX_ODLY_DQ_FINAL_BIT10                  int     true       96
BRAM_WRCMPLX_ODLY_DQ_FINAL_BIT11                  int     true       102
BRAM_WRCMPLX_ODLY_DQ_FINAL_BIT12                  int     true       96
BRAM_WRCMPLX_ODLY_DQ_FINAL_BIT13                  int     true       105
BRAM_WRCMPLX_ODLY_DQ_FINAL_BIT14                  int     true       99
BRAM_WRCMPLX_ODLY_DQ_FINAL_BIT15                  int     true       93
BRAM_WRCMPLX_ODLY_DQ_FINAL_BIT16                  int     true       78
BRAM_WRCMPLX_ODLY_DQ_FINAL_BIT17                  int     true       74
BRAM_WRCMPLX_ODLY_DQ_FINAL_BIT18                  int     true       72
BRAM_WRCMPLX_ODLY_DQ_FINAL_BIT19                  int     true       78
BRAM_WRCMPLX_ODLY_DQ_FINAL_BIT20                  int     true       65
BRAM_WRCMPLX_ODLY_DQ_FINAL_BIT21                  int     true       80
BRAM_WRCMPLX_ODLY_DQ_FINAL_BIT22                  int     true       76
BRAM_WRCMPLX_ODLY_DQ_FINAL_BIT23                  int     true       77
BRAM_WRCMPLX_ODLY_DQ_FINAL_BIT24                  int     true       33
BRAM_WRCMPLX_ODLY_DQ_FINAL_BIT25                  int     true       36
BRAM_WRCMPLX_ODLY_DQ_FINAL_BIT26                  int     true       39
BRAM_WRCMPLX_ODLY_DQ_FINAL_BIT27                  int     true       43
BRAM_WRCMPLX_ODLY_DQ_FINAL_BIT28                  int     true       37
BRAM_WRCMPLX_ODLY_DQ_FINAL_BIT29                  int     true       40
BRAM_WRCMPLX_ODLY_DQ_FINAL_BIT30                  int     true       42
BRAM_WRCMPLX_ODLY_DQ_FINAL_BIT31                  int     true       38
BRAM_WRCMPLX_ODLY_DQ_FINAL_BIT32                  int     true       77
BRAM_WRCMPLX_ODLY_DQ_FINAL_BIT33                  int     true       84
BRAM_WRCMPLX_ODLY_DQ_FINAL_BIT34                  int     true       78
BRAM_WRCMPLX_ODLY_DQ_FINAL_BIT35                  int     true       88
BRAM_WRCMPLX_ODLY_DQ_FINAL_BIT36                  int     true       82
BRAM_WRCMPLX_ODLY_DQ_FINAL_BIT37                  int     true       93
BRAM_WRCMPLX_ODLY_DQ_FINAL_BIT38                  int     true       85
BRAM_WRCMPLX_ODLY_DQ_FINAL_BIT39                  int     true       89
BRAM_WRCMPLX_ODLY_DQ_FINAL_BIT40                  int     true       78
BRAM_WRCMPLX_ODLY_DQ_FINAL_BIT41                  int     true       78
BRAM_WRCMPLX_ODLY_DQ_FINAL_BIT42                  int     true       80
BRAM_WRCMPLX_ODLY_DQ_FINAL_BIT43                  int     true       86
BRAM_WRCMPLX_ODLY_DQ_FINAL_BIT44                  int     true       80
BRAM_WRCMPLX_ODLY_DQ_FINAL_BIT45                  int     true       90
BRAM_WRCMPLX_ODLY_DQ_FINAL_BIT46                  int     true       78
BRAM_WRCMPLX_ODLY_DQ_FINAL_BIT47                  int     true       80
BRAM_WRCMPLX_ODLY_DQ_FINAL_BIT48                  int     true       96
BRAM_WRCMPLX_ODLY_DQ_FINAL_BIT49                  int     true       93
BRAM_WRCMPLX_ODLY_DQ_FINAL_BIT50                  int     true       91
BRAM_WRCMPLX_ODLY_DQ_FINAL_BIT51                  int     true       99
BRAM_WRCMPLX_ODLY_DQ_FINAL_BIT52                  int     true       95
BRAM_WRCMPLX_ODLY_DQ_FINAL_BIT53                  int     true       102
BRAM_WRCMPLX_ODLY_DQ_FINAL_BIT54                  int     true       98
BRAM_WRCMPLX_ODLY_DQ_FINAL_BIT55                  int     true       102
BRAM_WRCMPLX_ODLY_DQ_FINAL_BIT56                  int     true       64
BRAM_WRCMPLX_ODLY_DQ_FINAL_BIT57                  int     true       72
BRAM_WRCMPLX_ODLY_DQ_FINAL_BIT58                  int     true       75
BRAM_WRCMPLX_ODLY_DQ_FINAL_BIT59                  int     true       77
BRAM_WRCMPLX_ODLY_DQ_FINAL_BIT60                  int     true       70
BRAM_WRCMPLX_ODLY_DQ_FINAL_BIT61                  int     true       76
BRAM_WRCMPLX_ODLY_DQ_FINAL_BIT62                  int     true       73
BRAM_WRCMPLX_ODLY_DQ_FINAL_BIT63                  int     true       77
BRAM_WRCMPLX_ODLY_DBI_FINAL_BYTE0                 int     true       58
BRAM_WRCMPLX_ODLY_DBI_FINAL_BYTE1                 int     true       102
BRAM_WRCMPLX_ODLY_DBI_FINAL_BYTE2                 int     true       76
BRAM_WRCMPLX_ODLY_DBI_FINAL_BYTE3                 int     true       46
BRAM_WRCMPLX_ODLY_DBI_FINAL_BYTE4                 int     true       82
BRAM_WRCMPLX_ODLY_DBI_FINAL_BYTE5                 int     true       82
BRAM_WRCMPLX_ODLY_DBI_FINAL_BYTE6                 int     true       101
BRAM_WRCMPLX_ODLY_DBI_FINAL_BYTE7                 int     true       72
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