XSDB Registers of Interest during Write Latency Calibration

XSDB Registers of Interest during Write Latency Calibration - 1.0 English

Versal Adaptive SoC Soft DDR4 SDRAM Memory Controller LogiCORE IP Product Guide (PG353)

Document ID

PG353

Release Date

2023-10-18

Version

1.0 English

The following table shows the XSDB registers and values adjusted or used during the Write Latency stage of calibration. The values can be analyzed in both successful and failing calibrations to determine the resultant values and the consistency in results across resets. These values can be found within the Memory IP core properties in the Hardware Manager or by executing the Tcl commands noted in the Manually Analyzing the XSDB Output section.

Table 1. XSDB Registers of Interest during Write Latency Calibration
XSDB Reg	Usage	Signal Description
BRAM_WRLAT_INIT_LATENCY	One value	Global initial write latency value.
BRAM_WRLAT_MATCH_RANK_BYTE	One per byte	Common Write Latency across all ranks.
BRAM_WRLAT_MIN_LATENCY	One value	Minimum Write Latency across all ranks.
BRAM_WRLAT_WLDLYRNK_CRSE_FINAL_RANK_BYTE	One per rank per byte	Final WR_DLY_RNK* coarse tap setting after write leveling.

This is a sample of the results for the Write Latency XSDB debug signals:

BRAM_WRLAT_INIT_LATENCY                       int     true       0
BRAM_WRLAT_MATCH_RANK0_BYTE0                  int     true       0
BRAM_WRLAT_MATCH_RANK0_BYTE1                  int     true       0
BRAM_WRLAT_MATCH_RANK0_BYTE2                  int     true       0
BRAM_WRLAT_MATCH_RANK0_BYTE3                  int     true       0
BRAM_WRLAT_MATCH_RANK0_BYTE4                  int     true       0
BRAM_WRLAT_MATCH_RANK0_BYTE5                  int     true       0
BRAM_WRLAT_MATCH_RANK0_BYTE6                  int     true       0
BRAM_WRLAT_MATCH_RANK0_BYTE7                  int     true       0
BRAM_WRLAT_MIN_LATENCY                        int     true       0
BRAM_WRLAT_WLDLYRNK_CRSE_FINAL_RANK0_BYTE0    int     true       0
BRAM_WRLAT_WLDLYRNK_CRSE_FINAL_RANK0_BYTE1    int     true       0
BRAM_WRLAT_WLDLYRNK_CRSE_FINAL_RANK0_BYTE2    int     true       0
BRAM_WRLAT_WLDLYRNK_CRSE_FINAL_RANK0_BYTE3    int     true       0
BRAM_WRLAT_WLDLYRNK_CRSE_FINAL_RANK0_BYTE4    int     true       0
BRAM_WRLAT_WLDLYRNK_CRSE_FINAL_RANK0_BYTE5    int     true       0
BRAM_WRLAT_WLDLYRNK_CRSE_FINAL_RANK0_BYTE6    int     true       6
BRAM_WRLAT_WLDLYRNK_CRSE_FINAL_RANK0_BYTE7    int     true       6