app_addr[APP_ADDR_WIDTH - 1:0] - 1.0 English

Versal Adaptive SoC Soft DDR4 SDRAM Memory Controller LogiCORE IP Product Guide (PG353)

Document ID
PG353
Release Date
2023-10-18
Version
1.0 English

This input indicates the address for the request currently being submitted to the user interface. The user interface aggregates all the address fields of the external SDRAM and presents a flat address space.

The MEM_ADDR_ORDER parameter determines how app_addr is mapped to the SDRAM address bus and chip select pins. This mapping can have a significant impact on memory bandwidth utilization. “ROW_COLUMN_BANK” is the recommended MEM_ADDR_ORDER setting. The following tables show the “ROW_COLUMN_BANK” mapping for DDR4 with examples. Note that the three LSBs of app_addr map to the column address LSBs which correspond to SDRAM burst ordering.

The controller does not support burst ordering so these low order bits are ignored, making the effective minimum app_addr step size hex 8.