Calibration Status Register Signal Descriptions - 1.0 English

Versal ACAP Soft RLDRAM 3 Memory Controller LogiCORE IP Product Guide (PG354)
Document ID
PG354
Release Date
2021-11-03
Version
1.0 English
Table 1. Calibration Status Register Signal Descriptions
Status Register Bits Description
cal_passed_stages[31:0] 0 PHY ready asserted
1 RLDRAM 3 Initialization completed
2 CA Calibration completed
3 Simple Read Calibration completed
4 Simple Write Calibration completed
5 Write Latency Calibration completed
6 Read Latency Calibration completed
7 Complex Read Calibration completed
8 Complex Write Calibration completed
31:9 Reserved
cal_failed_stages[31:0] 0 PHY ready failed to assert
1 RLDRAM 3 Initialization failed to complete
2 CA Calibration failed to complete
3 Simple Read Calibration failed to complete
4 Simple Write Calibration failed to complete
5 Write Latency Calibration failed to complete
6 Read Latency Calibration failed to complete
7 Complex Read Calibration failed to complete
8 Complex Write Calibration failed to complete
31:9 Reserved
cal_skipped_stages[31:0] 0 Always set to 0 because PHY ready is never skipped
1 Always set to 0 because RLDRAM 3 Initialization is never skipped
2 Set to 1 when CA Calibration is skipped
3 Set to 1 when Simple Read Calibration is skipped
4 Set to 1 when Simple Write Calibration is skipped
5 Always set to 0 because Write Latency Calibration is never skipped
6 Always set to 0 because Read Latency Calibration is never skipped
7 Complex Read Calibration skipped (set to 1) below 800 MHz
8 Complex Write Calibration skipped (set to 1) below 800 MHz
31:9 Reserved