Command/Address Calibration - 1.0 English

Versal ACAP Soft RLDRAM 3 Memory Controller LogiCORE IP Product Guide (PG354)

Document ID
PG354
Release Date
2021-11-03
Version
1.0 English
In Command/Address (CA) calibration stage, ODELAY of address and command signals are adjusted to center the rising edge of CK in valid region of address and command signals.

The CA calibration steps are listed as follows:

  1. At the start of CA calibration, PDQS and NDQS of all the nibbles are delayed together until the PDQS of each nibble finds valid stable region for each bit of its nibble once. In CA calibration, valid data on the DQ bus indicates valid stable region for the CA bus.
  2. ODELAY of each address and command bits are incremented by 10 taps and step 1 is repeated.
  3. Step 1 and step 2 are repeated until you have a valid region for continuous 200 taps ODELAY increment of address and command bits.
  4. ODELAY of each address and command bits are adjusted such that rising edge of CK is placed at the center of valid region.