Required Constraints
This section is not applicable for this IP core.
Device, Package, and Speed Grade Selections
This section is not applicable for this IP core.
Clock Frequencies
This section is not applicable for this IP core.
Clock Management
This section is not applicable for this IP core.
Clock Placement
This section is not applicable for this IP core.
Banking
This section is not applicable for this IP core.
Transceiver Placement
This section is not applicable for this IP core.
I/O Standard and Placement
The RLDRAM 3 tool generates the appropriate I/O standards and placement based on the selections made in the Vivado IDE for the interface type and options.
Important: The
set_input_delay
and set_output_delay
constraints are not needed on the external memory interface pins in this design due
to the calibration process that automatically runs at start-up. Warnings seen during
implementation for the pins can be ignored.