This section describes the Xilinx® Versal® adaptive compute acceleration platform (ACAP) Memory Interface Solutions core with an overview of the modules and interfaces. The core is shown below.
The user interface uses a simple protocol based entirely on SDR signals to make read and write requests. See the User Interface section for more details describing this protocol.
The Memory Controller takes commands from the user interface and adheres to the protocol requirements of the RLDRAM 3 device. See the Memory Controller section for more details.
The physical interface generates the proper timing relationships and DDR signaling to communicate with the external memory device, while conforming to the RLDRAM 3 protocol and timing requirements. See the Physical Interface section for more details.