Core Overview - 1.0 English

The RLDRAM 3 core provides solutions for interfacing with the DRAM memory type. The Versal ACAP for the RLDRAM 3 core are organized in the following high-level blocks:

Controller

The controller accepts burst transactions from the user interface and generates transactions to and from the RLDRAM 3. The controller takes care of the DRAM timing parameters and refresh.

Physical Layer

The physical layer provides a high-speed interface to the DRAM. This layer includes the hard blocks inside the Versal ACAP and the soft calibration logic blocks necessary to ensure optimal timing of the hard blocks interfacing to the DRAM.

The new hard blocks in the Versal ACAP allow interface rates of up to 2,400 Mb/s to be achieved. These hard blocks include:

• Data serialization and transmission
• Data capture and deserialization
• High-speed clock generation and synchronization
• Fine delay elements per pin with voltage and temperature tracking

The soft blocks include:

Memory Initialization

The calibration modules provide an initialization routine for RLDRAM 3. The delays in the initialization process are bypassed to speed up simulation time.

Calibration

The calibration modules provide a complete method to set all delays in the hard blocks and soft IP to work with the memory interface. Each bit is individually trained and then combined to ensure optimal interface performance.

Results of the calibration process are available through the Xilinx® debug tools. After completion of calibration, the PHY layer presents raw interface to the DRAM.

Application Interface

The user interface layer provides a simple FIFO-like interface to the application. Data is buffered and read data is presented in request order.