There are two types of debug signals used in Memory IP Versal ACAP debug. The first set is a part of a debug interface that
is always included in generated Memory IP Versal
ACAP designs. These signals include init_calib_complete and
calib_error.
The second type of debug signals are fully integrated in the IP when you enable the Debug Signals option in the Memory IP tool and when using the Memory IP Example Design. These signals are connected to the debug ILA core.