Features - 1.0 English

Versal ACAP Soft RLDRAM 3 Memory Controller LogiCORE IP Product Guide (PG354)

Document ID
PG354
Release Date
2021-11-03
Version
1.0 English
  • Component support for interface widths of 18, 36, and 72 bits
    Table 1. Supported Configurations
    Interface Width Burst Length Number of Device
    36 BL2, BL4 1, 2
    18 BL2, BL4, BL8 1, 2
    36 with address multiplexing BL2, BL4 1, 2
    18 with address multiplexing BL2, BL4, BL8 1, 2
  • ODT support
  • Memory device support with 576 Mb and 1.125 Gb densities
  • RLDRAM 3 initialization support
  • Source code delivery in Verilog
  • 4:1 memory to Versal ACAP logic interface clock ratio
  • Interface calibration and training information available through the Vivado® hardware manager