The width of certain user interface signals is dependent on the burst length. This allows the client to send multiple commands per Versal ACAP logic clock cycle as might be required for certain configurations.
The user interface protocol for the RLDRAM 3 four-word burst architecture is shown in the following figure.
Before any requests can be accepted, the
ui_clk_sync_rst signal must be deasserted Low. After the
ui_clk_sync_rst signal is deasserted, the user interface FIFOs can
accept commands and data for storage. The init_calib_complete signal is
asserted after the memory initialization procedure and PHY calibration are complete, and
the core can begin to service client
requests.
The user interface provides an interface for you to communicate with
the RLDRAM 3 controller. To assert any command,
you must assert user_cmd_en as a single cycle pulse.
At this time, user_cmd, user_addr, and user_ba must be valid. If
the output signal, user_afifo_full is asserted then
user_cmd_en is ignored and no commands are
accepted at that clock edge. The assertion of user_afifo_full signal indicates to you that the command/address FIFO is
full and no further commands can be accepted. The user_wr_en signal, when asserted indicates that the user_wr_data and user_wr_dm signals must be valid at this time. If the user_wdiffo_full signal is 1, the user_wr_en signal is ignored. The user_rd_valid signal indicates that user_rd_data is valid on the respective channel.
The controller performs reordering of the commands before sending them out to the memory device to improve efficiently. Therefore, commands at the memory device might not be in the same order as it was received. However, the read response is in the same order as the input read commands requested by you.
The previous figure shows the protocol for the BL2 interface. With
BL2, you are allowed to send four commands at the rising edge of the user clock. When
the user_cmd_en signal is 1, the user_cmd, user_addr, and
user_ba signals are accepted by the user
interface. However when the user_afifo_full signal is
asserted shown as the shaded region, all commands are ignored. The commands at the
user_cmd signal input can be mix of write, read,
NOP, or refresh commands. There are no restrictions which commands can be sent on a
particular channel. As shown in the following figure, CMD3 and CMD1 could be write
commands, CMD0 could be a read command, and CMD2 could be a NOP command.
The write data (user_wr_data) and
write data mask (user_wr_mask) signals for a write
command in a channel must be valid when the user_wr_en
signal for that channel is asserted. If the corresponding user_wdfifo_full signal is 1, then the user_wr_en signal of that channel is ignored. As shown in the previous
figure, when the user_wdfifo_full signal of channels 1
and 3 are asserted write data and mask signals are ignored.
The user_rd_valid signal when
asserted indicates valid read data (user_rd_data) from
the corresponding channel. As shown in the previous figure, valid user read data is
available on channels 3 and 1, as indicated by user_rd_valid[3] and user_rd_valid[1]
signals.
Also, the same protocol is applicable for BL4 and BL8 interfaces. One difference is that the number of commands per clock or the number of channels will be reduced to 2 and 1 for BL4 and BL8, respectively. The write and read data width per channel will increase by 2 and 4 times for BL4 and BL8, respectively.