The Xilinx® Versal® adaptive compute acceleration platform (ACAP) Memory IP core is a combined pre-engineered controller and physical layer (PHY) for interfacing Versal ACAP user designs to RLDRAM 3 devices.
The Xilinx® Versal® adaptive compute acceleration platform (ACAP) Memory IP core is a combined pre-engineered controller and physical layer (PHY) for interfacing Versal ACAP user designs to RLDRAM 3 devices.