Memory IPs provide a possibility to select the Reference Input Clock Speed. The value allowed for Reference Input Clock Speed (ps) is always ≥ Memory Device Interface Speed (ps). Memory IP lists the possible Reference Input Clock Speed values based on the targeted memory frequency (based on selected Memory Device Interface Speed).
The required Reference Input Clock Speed is calculated from the M, D, and O values entered in the GUI using the following formulas:
- XPLL_CLKOUT (MHz) = tCK / Phy_Clock_Ratio
Where tCK is the Memory Device Interface Speed selected in the Basic tab.
- CLKIN (MHz) = (XPLL_CLKOUT (MHz) × D × O) / M
CLKIN (MHz) is the calculated Reference Input Clock Speed.
- VCO (MHz) = (CLKIN (MHz)) / D
VCO (MHz) is the calculated VCO frequency.
Calculated Reference Input Clock Speed from M, D, and O values are validated as per clocking guidelines. For more information on clocking rules, see the Clocking section.
Apart from the memory specific clocking rules, validation of the possible XPLL input frequency range and XPLL VCO frequency range values are completed for M, D, and O in the GUI.
For Versal Prime series, see the Versal Prime Series Data Sheet: DC and AC Switching Characteristics (DS956) for XPLL Input frequency range and XPLL VCO frequency range values.
For Versal AI Core series, see the Versal AI Core Series Data Sheet: DC and AC Switching Characteristics (DS957) for XPLL Input frequency range and XPLL VCO frequency range values.
For possible M, D, and O values and detailed information on clocking and the XPLL, see the Versal ACAP Clocking Resources Architecture Manual (AM003).