Memory Initialization and Calibration Sequence - 1.0 English

After deassertion of the system reset, the PHY performs some required internal calibration steps first.

1. The built-in self-check (BISC) of the PHY is run. BISC is used in the PHY to compute internal skews for use in voltage and temperature tracking after calibration is completed.
2. After BISC is completed, calibration logic performs the required power-on initialization sequence for the memory.
3. When both routines are finished, the control is transferred to MicroBlaze™ , which is a soft processor that calibrates the timing of the write and read data paths.
4. After calibration is completed, the PHY calculates internal offsets to be used in voltage and temperature tracking.

The following figure shows the overall flow of memory initialization and the different stages of calibration.

When simulating the RLDRAM 3 example design, the calibration process is bypassed to allow for quick traffic generation to and from the RLDRAM 3 device. Calibration is always enabled when running the example design in hardware. The hardware manager GUI provides information on the status of each calibration step or description of error in case of calibration failure.

If the hardware manager GUI is not used, the first step in determining the calibration status is to check the status of init_calib_complete and calib_error signals. The init_calib_complete only asserts if calibration passes successfully, otherwise calib_error is asserted. Calibration halts on the very first error encountered. There are three status registers, cal_passed_stages, cal_failed_stages, and cal_skipped_stages that provide information on the successfully completed calibration stages, the failed stages, and the skipped stages, respectively.