The Versal ACAP PHY is composed of dedicated blocks and soft calibration logic. The dedicated blocks are structured adjacent to one another with back-to-back interconnects to minimize the clock and datapath routing necessary to build high performance physical layers.
The MC and calibration logic communicate with this dedicated PHY in the slow frequency clock domain, which is divided by 4. A more detailed block diagram of the PHY design is shown in the Core Architecture.
The MC is designed to separate out the command processing from the low-level PHY requirements to ensure a clean separation between the controller and physical layer. The command processing can be replaced with custom logic if desired, while the logic for interacting with the PHY stays the same and can still be used by the calibration logic.
| Module Name | Description |
|---|---|
| rld3_pl_0.sv | RLDRAM 3 top module |
| rld3_pl_0_rld3_mem_intfc.sv | This is the module where the PHY, controller, and calibration modules are instantiated. The modules which correct the bitslips and address pipe modules are also instantiated here. |
| rld3_pl_0_phy.sv | This is the top module of the XPHY where the XPLL and bank wrapper modules are instantiated. |
| rld3_pl_phy_v1_0_pll.sv | PLL module where the XPLLs are instantiated. |
| rld3_pl_phy_v1_0_xphy_bank_wrapper.sv | Bank wrapper module which contains the instantiation of the XPHY banks. |
| rld3_pl_phy_v1_0_xphy_bank.sv | XPHY bank module |
| rld3_pl_v1_0_cmd_addr_pi.sv | This module adds the necessary delay on to the address and control signals that is going to the memory interface to match the latency and calibration requirements. |
| rld3_pl_v1_0_data_pi.sv | This module adds the necessary delay on the data and dm that is going to the memory interface to match the latency and calibration requirements. |
| rld3_pl_v1_0_cal_top.sv | Calibration top module |
| rld3_pl_v1_0_cal_addr_decode.sv | This module interacts with C code to do the necessary calibration related operations. This contains the necessary register space for calibration. |
The PHY architecture encompasses all of the logic contained in rld_xphy.sv. The PHY contains wrappers around dedicated hard blocks to build up the memory interface from smaller components. A byte lane contains all of the clocks, resets, and datapaths for a given subset of I/O. Multiple byte lanes are grouped together, along with dedicated clocking resources, to make up a single bank memory interface. For more information on the hard silicon physical layer architecture, see the Versal ACAP SelectIO Resources Architecture Manual (AM010).