The physical interface is the connection from the Versal ACAP core to an external RLDRAM 3 device. The I/O signals for this interface are defined in the table. These signals can be directly connected to the corresponding signals on the RLDRAM 3 device.
Signal | I/O | Description |
---|---|---|
rld_ck_p | O | System Clock CK. This is the address/command clock to the memory device. |
rld_ck_n | O | System Clock CK#. This is the inverted system clock to the memory device. |
rld_dk_p | O | Write Clock DK. This is the write clock to the memory device. |
rld_dk_n | O | Write Clock DK#. This is the inverted write clock to the memory device. |
rld_a | O | Address. This is the address supplied for memory operations. |
rld_ba | O | Bank Address. This is the bank address supplied for memory operations. |
rld_cs_n | O | Chip Select CS#. This is the active-Low chip select control signal for the memory. |
rld_we_n | O | Write Enable WE#. This is the active-Low write enable control signal for the memory. |
rld_ref_n | O | Refresh REF#. This is the active-Low refresh control signal for the memory. |
rld_dm | O | Data Mask DM. This is the active-High mask signal, driven by the core ACAP to mask data that a user does not want written to the memory during a write command. |
rld_dq | I/O | Data DQ. This is a bidirectional data port, driven by the core ACAP for writes and by the memory for reads. |
rld_qk_p | I | Read Clock QK. This is the read clock returned from the memory edge aligned with read data on rld_dq. This clock (with QK#) is used by the PHY to sample the read data on rld_dq. |
rld_qk_n | I | Read Clock QK#. This is the inverted read clock returned from the memory. This clock (with QK) is used by the PHY to sample the read data on rld_dq. |
rld_reset_n | O | RLDRAM 3 reset pin. This is the active-Low reset to the RLDRAM 3 device. |