Pin and Bank Rules - 1.0 English

Versal ACAP Soft RLDRAM 3 Memory Controller LogiCORE IP Product Guide (PG354)

Document ID
PG354
Release Date
2021-11-03
Version
1.0 English
The rules are for single-rank memory interfaces.
Important: The Versal ACAP soft memory IP can only use XPIO pins that are fully fabric accessible. Refer to the package file to determine XPIO pins that are fully fabric accessible. The XPIO pins/banks in a Versal device that are not fabric accessible are called shadow pins/banks.
  • Address/control means cs_n, ref_n, we_n, ba, ck, reset_n, and a.
  • Each bank has nine nibbles numbered 0 to 8. Two consecutive nibbles in a bank are paired to form a nibble pair. For example, 0-1, 2-3, 4-5, and 6-7 are the four nibble pairs in a bank.
  • Pins in a nibble are numbered 0 to 5. For example in the package pin name IO_L0N_XCC_N0P1_M0P1_700, N0P1 indicates pin 1 of nibble 0 in bank 700.
Note: There are two XPLLs per bank and one XPLL is required in every bank that is being used for the memory interface.
  1. For 1x18 pin rules:
    1. All signals for this interface must be placed in two consecutive banks.
    2. All data associated with a Write clock pair (dk_p/n) must be placed in the same bank.
    3. A data group comprising of nine dq bits, one Read clock pair (qk_p/n), and one DM must be placed in two consecutive nibbles. The Read clock pair (qk_p/n) can be placed in any one of the two nibbles.
    4. DQ bits must only be placed in nibbles 2, 3, 4, and 5.
    5. qk_p/n must be assigned to pin pair 0/1 in a nibble.
    6. Write clock pairs dk_p/n[0] and dk_p/n[1] and memory clock pair (ck_p/n) must be placed in nibble 8.
    7. Memory clock pair (ck_p/n) must be placed in pin pair 2/3 of nibble 8.
    8. Write clock pairs dk_p/n[*] must be placed in pin pairs closest to the adjacent nibble with its associated data group as shown in the 1x18 pinout example.
    9. Address and command pin rules:
      • Skipping nibbles between address and data groups is not allowed.
      • Free nibbles in the data bank and nibbles 0 or 7 of the adjacent bank can be used for Address/Control. If the adjacent bank is on right side of the data bank, nibble 0 must be used else nibble 7 must be used for address/control as shown in the 1x18 pinout example.
  2. For 2x18 pin rules:
    1. All signals for this interface must be placed in two consecutive banks.
    2. All data associated with a Read clock pair (qk_p/n) must be placed in the same bank.
    3. A data group comprising of nine dq bits, one Read clock pair (qk_p/n), and one DM should be placed in two consecutive nibbles.
    4. The Read clock pair (qk_p/n) must be assigned to pin pair 0/1 in any one of the two nibbles.
    5. Write clock pairs dk_p/n[*] and memory clock pair (ck_p/n) must be placed in three contiguous nibbles in the Address/control bank as shown in the 2x18 example pinout.
    6. Memory clock pair (ck_p/n) must be placed in pin pair 2/3 of nibble 8.
    7. No other signals or free pins allowed between ck_p/n and dk_p/n pairs.
    8. All Address/control signals must be in a single bank.
  3. For 1x36 pin rules:
    1. All signals for this interface must be placed in two consecutive banks.
    2. A data group comprising of nine DQ bits, and one Read clock pair (qk_p/n) must be placed in two consecutive nibbles. The Read clock pair (qk_p/n) must be placed on pin pairs 0/1 in any one of the two nibbles.
    3. All DQ bits must be placed in a single bank.
    4. 18 bits data group comprising of 18 DQ bits and one DM must be placed in four consecutive nibbles. DM can be placed in any of the four nibbles.
    5. Write clock pairs dk_p/n[0] and dk_p/n[1] and memory clock pair (ck_p/n) must be placed in nibble 8.
    6. Memory clock pair (ck_p/n) must be placed in pin pair 2/3 of nibble 8.
    7. Write clock pairs dk_p/n[*] must be placed in pin pairs closest to the adjacent nibble with its associated data group as shown in the 1x18 pinout example.
    8. Address and command pin rules:
      • Skipping nibbles between address and data groups is not allowed.
      • Address/Control must be placed in five consecutive nibbles in a bank adjacent to the data bank. If the adjacent bank is on right side of the data bank, nibbles 0, 1, 2, 3, and 8 must be used else nibbles 8, 4, 5, 6, and 7 must be used for address/control as shown in the 1x36 example pinout.
  4. For 2x36 pin rules:
    1. All signals for this interface must fit in three consecutive banks.
    2. A data group comprising of nine DQ bits, and one Read clock pair (qk_p/n) must be placed in two consecutive nibbles. The Read clock pair (qk_p/n) must be placed on pin pairs 0/1 in any one of the two nibbles.
    3. All DQ bits must only be placed in the first and third banks, not the middle bank.
    4. 18 bits data group comprising of 18 DQ bits and one DM must be placed in four consecutive nibbles. DM can be placed in any of the four nibbles.
    5. Memory clock pair (ck_p/n) must be placed in pin pair 2/3 of nibble 8 in the middle bank.
    6. Write clock pairs dk_p/n[*] must be placed in pin pairs closest to the adjacent nibble with its associated data group as shown in the 2x36 example pinout.
    7. No other signals or free pins allowed between ck_p/n and dk_p/n pairs.
    8. All Address/control signals must be in the middle bank.
  5. The IO_VP pin is an additional bank pin that is used as a reference to calibrate internal on-die termination (DCI). This pin must be externally connected to a 240Ω resistor on the PCB and pulled up to the bank VCCO voltage. DCI is required for this interface. All rules for the DCI in the Versal ACAP SelectIO Resources Architecture Manual (AM010) must be followed.
  6. The reset_n can be placed on any available pin within the banks used by the interface.
  7. Banks can be shared between two controllers.
    • Each byte lane is dedicated to a specific controller (except for reset_n).
    • Byte lanes from one controller cannot be placed inside the other. For example, with controllers A and B, “AABB” is allowed, while “ABAB” is not.
  8. All I/O banks used by the memory interface must be in the same SLR of the column for the SSI technology devices.
  9. Maximum height of interface is three contiguous banks for 72-bit wide interface.
  10. Bank skipping is not allowed.
  11. The input clock for the XPLL in the interface must come from the a GCIO pair within the banks used for the memory interface. Information on the clock input specifications can be found in the AC and DC Switching Characteristics data sheets (LVDS input requirements should be considered). For more information, see the Clocking section.
  12. Versal ACAP XPIO only supports internally generated VREF. See the Versal ACAP SelectIO Resources Architecture Manual (AM010) for details.
  13. RLDRAM 3 pins not mentioned in the cited pin rules (JTAG, MF, etc.) or ones that you choose not to use in your design must be connected as per Micron® RLDRAM 3 data sheet specification.
  14. The system reset pin (sys_rst_n) can be placed on any pin within the banks used for the memory interface.
    Important: RLDRAM 3 IP does not support output data valid indicator. Contact your memory vendor for terminating QVLD# at memory.