This method can be used to simulate the example design using the Vivado Design Suite (IDE). Memory IP delivers IEEE encrypted memory models for RLDRAM 3.
The Vivado simulator, Questa Advanced Simulator, IES, and VCS tools are used for RLDRAM 3 IP verification at each software release. The Vivado simulation tool is used for RLDRAM 3 IP verification from 2021.2 Vivado software release. The following subsections describe steps to run a project-based simulation using each supported simulator tool.