RLDRAM 3 Debug Signals Used in Vivado Design Suite Debug Feature - 1.0 English

Versal ACAP Soft RLDRAM 3 Memory Controller LogiCORE IP Product Guide (PG354)

Document ID
PG354
Release Date
2021-11-03
Version
1.0 English

The following table shows the RLDRAM 3 debug signals.

Table 1. RLDRAM 3 Debug Signals Used in Vivado Design Suite Debug Feature
Signal Signal Width Signal Description
init_calib_complete   Signifies the status of calibration.

1’b0 = Calibration not complete

1’b1 = Calibration completed successfully

calib_error [0:0][0:0] Signifies the status of calibration.

1’b0 = Calibration error not detected

1’b1 = Calibration error detected

cal_passed_stages [31:0] Contains information of the completed calibration stages.
cal_failed_stages [31:0] Contains information of failed calibration stages.
cal_skipped_stages [31:0] Contains information of skipped calibration stages.