To maximize the data eye and center the internal read sampling clock in the read DQ
window for robust sampling, the following steps are performed:
- Per bit deskew of the DQ bus to maximize the data eye by removing skew and On-Chip Variation effects.
- Sweep internal read clock and its inverse across all DQ bits to find the center of the rise and fall data eyes.
- The read clock, QK is delayed using the PQTR and NQTR delay taps to generate the internal read clock and its inverse, respectively.
- For this stage of calibration, a pre-defined
1010...pattern is read from Mode Register 2 in the RLDRAM 3 device because the write path has not yet been calibrated. The per bit deskew step begins with simultaneously incrementing PQTR and NQTR until the internal read clocks and their inverse are in the valid data region. - IDELAY taps for all DQ bits are incremented until invalid data is sampled on each bit thereby deskewing DQ bits with its associated read clock and its inverse.
- Read clocks and their inverse are moved using PQTR and NQTR delay taps to detect the valid window edges and then centered in the valid window.